ABSTRACT
Minimizing power dissipation is an important design requirement for both portable and non-portable systems. In this work, we propose an architectural solution to the power problem that retains performance while reducing power. The technique, known as Pipeline Balancing (PLB), dynamically tunes the resources of a general purpose processor to the needs of the program by monitoring performance within each program. We analyze metrics for triggering PLB, and detail instruction queue design and energy savings based on an extension of the Alpha 21264 processor. Using a detailed simulator, we present component and full chip power and energy savings for single and multi-threaded execution. Results show an issue queue and execution unit power reduction of up to 23% and 13%, respectively, with an average performance loss of 1% to 2%.
- 1.D. Albonesi. Dynamic IPC/clock rate optimization. In Proceedings of the International Symposium on Computer A rchitecture, June 1998. Google ScholarDigital Library
- 2.D. Albonesi. Selective cache ways: On-demand cache resource allocation. In Proceedings of the International Symposium on Microarchitecture, November 1999. Google ScholarDigital Library
- 3.V. Arasanipalai. Private communication, Compaq Computer Corporation.Google Scholar
- 4.T. Burd Processor design for portable systems. Journal of VLSI Signal Processing, August 1996. Google ScholarDigital Library
- 5.G. Chrysos and J. Emer. Memory dependence prediction using store sets. In Proceedings of the International Symposium on Computer Architecture, June 1998. Google ScholarDigital Library
- 6.Compaq Computer Corporation. Alpha 21264 Microprocessor Hardware Reference Manual, July 1999.Google Scholar
- 7.Compaq Computer Corporation. The AS1M Manual, August 2000.Google Scholar
- 8.J.L. Cruz, A. Gonzalez, M. Valero, and N. Topham. Multiplebanked register file architectures. In Proceedings of the International Symposium on Computer Architecture, June 2000. Google ScholarDigital Library
- 9.J. A. Farrell and T. C. Fischer. Issue logic for a 600-mhz outof-order execution microprocessor. IEEE Journal of Solid- State Circuits, May 1998.Google Scholar
- 10.S. Ghiasi, J. Casmira, and D. Grunwald. Using 1PC variation in workloads with externally specified rates to reduce power consumption. In Workshop on Complexi~. -Effective Design, June 2000. Held in conjunction with the International Symposium on Computer Architecture.Google Scholar
- 11.P. N. Glaskowsky. Pentium 4 (partially) previewed. Microprocessor Report, August 2000.Google Scholar
- 12.M. K. Gowan, L. L. Biro, and D. B. Jackson. Power considerations in the design of the alpha 21264 microprocessor. In Proceedings of the Design Automation Conference ( DAC), June 1998. Google ScholarDigital Library
- 13.D. Grunwald, A. Klauser, S. Manne, and A. Pleszkun. Confidence estimation for speculation control. In Proceedblgs of the International Symposium on Computer Architecture, June 1998. Google ScholarDigital Library
- 14.S. Manne, A. Klauser, and D. Grunwald. Pipeline gating: Speculation control for energy reduction. In Proceedings of the International Symposium on Computer Architecture, June 1998. Google ScholarDigital Library
- 15.J. S. Seng, D. M. Tullsen, and G. Z. N. Cai. Power-sensitive multithreaded architecture. In Proceedings of the International Conference on Computer Design, October 2000. Google ScholarDigital Library
- 16.A. Snavely and D. M. Tullsen. Symbiotic jobscheduling lor a simultaneous multithreading architecture. In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), November 2000. Google ScholarDigital Library
- 17.D. W. Wall. Limits of instuction-level parallelism. In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), November 1991. Google ScholarDigital Library
- 18.K. Wilcox and S. Manne. Alpha processors: A history of power issues and a look to the future. In Cool-Chips Tutorial, November 1999. Held in conjunction with the International Symposium on Microarchitecture.Google Scholar
Index Terms
- Power and energy reduction via pipeline balancing
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Power and energy reduction via pipeline balancing
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