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The X architecture: not your father's diagonal wiring

Published:06 April 2002Publication History

ABSTRACT

The X Architecture is an integrated-circuit wiring architecture based on the pervasive use of diagonal wires. Compared with the traditional, currently ubiquitous, Manhattan architecture, the X Architecture demonstrates a wire length reduction of more than 20% and a via reduction of more 30%. Because of the rapidly increasing percentage of delay due to interconnect and the manufacturing challenges due to vias in the nanometer realm, these length and via reductions result simultaneously in a chip performance improvement of 10%, a power reduction of 20%, and a die cost reduction of 30%. Furthermore, the reduction in both wire length and parallel runs on different layers often both reduces die size and improves signal integrity. Remarkably, on virtually every important measure of chip quality, the X Architecture is superior to the Manhattan architecture.While diagonal wiring has been discussed for years, and short diagonal jogs have even been used for years, pervasive diagonal wiring has not been used on an IC before 2002 (to our knowledge). The fundamental reasons for this are not manufacturing limitations, as might be suspected, but EDA limitations, and the changes required to take full advantage of the X Architecture are significant and numerous. In particular, routing must be not only octilinear, but also gridless and non-preferred direction. In addition, significant changes are required at least in floorplanning, placement, global routing, extraction, power routing, clock routing, wire length estimation (e.g., in synthesis), database, graphics, and even data interchange formats. The folklore that 45-degree wiring might not be worth the trouble because it can provide only a 10% reduction in wire length is rooted in the incorrect assumptions that (a) only the router must change, (b) the router must resemble contemporary, preferred-direction, net-at-a-time maze routers, and (c) that wire length is the only major contributor to interconnect delay.In this short paper, we present some of the challenges and opportunities afforded by the X Architecture and show some early results that demonstrate the promise of pervasive, diagonal wiring, reflecting our belief that five years from now, virtually all, high-performance, integrated circuits will use the X Architecture.

References

  1. 1.International Technology Roadmap for Semiconductors, 2001 Edition - Interconnect http://public.itrs.net/Files/2001ITRS/Interconnect.pdfGoogle ScholarGoogle Scholar
  2. 2.http://www.research.ibm.com/resources/press/strainedsilic on/Google ScholarGoogle Scholar
  3. 3.http://www.xinitiative.org/Google ScholarGoogle Scholar
  4. 4.SDA Systems Edge product, c. 1986Google ScholarGoogle Scholar
  5. 5.E. Lodi, "Routing multiterminal nets in a diagonal model," Proceedings of the 1988 Conference on Information Sciences and Systems, Dept. of EE, Princeton University, pp. 899-902Google ScholarGoogle Scholar
  6. 6.N. Kuwahara et al., "A routing system for highperformance computer systems," Proc. ICCAD '86, pp. 250-253, 1986Google ScholarGoogle Scholar
  7. 7.Paul de Dood, John Wawrzynek, Erwin Liu, Roberto Suaya: A Two-Dimensional Topological Compactor With Octagonal Geometry. DAC 1991, pp. 727-731. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. 8.C. Chiang and M. Sarrafzadeh, "Wirability of Knock-knee Layouts with 45-degree Wires," IEEE Transactions on Circuits & Systems, Vol. 38, No. 6, June 1991, pp. 613-624.Google ScholarGoogle ScholarCross RefCross Ref
  9. 9.M. Igarashi, Toshiba Corp., personal communication.Google ScholarGoogle Scholar
  10. 10.H. Samet. The Design and Analysis of Spatial Data Structures, Addison-Wesley, 1990. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. 11.U.S. Patent 4,673,966.Google ScholarGoogle Scholar

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  1. The X architecture: not your father's diagonal wiring

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              Ion I Mandoiu

              Diagonal interconnect used to be common at the beginning of the integrated circuit era, when circuit layout was done at the drawing board. Diagonal wires disappeared almost completely in the early eighties, when for the sake of efficiency, emerging physical design automation tools chose to support only rectilinear interconnect. Almost two decades later, a major industry effort is aimed at reintroducing the pervasive use of diagonal wires. In this invited paper, Steven Teig, one of the key architects of the so-called “X architecture,” gives an overview of the challenges and opportunities afforded by the pervasive use of diagonal interconnect. Teig argues that taking full advantage of the X architecture requires numerous and significant changes to current design automation tools. Besides detailed routing (which must become gridless and non-preferred direction, with accurately modeled via costs), significant changes are required in floorplanning, placement, global routing, extraction, power and clock routing, wire length estimation, graphics and database, and even data interchange formats. However, these changes seem to be well worth the effort: commercial designs replaced and rerouted with the X architecture show simultaneous improvements in virtually every important measure of chip quality, including 20 percent wire length and power reductions and 30 percent via count and die cost reductions, as well as more than 10 percent performance improvement. Teig concludes that these improvements are too important to be ignored, and that in a few years, all high-performance integrated circuits will use the X architecture. Online Computing Reviews Service

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                cover image ACM Conferences
                SLIP '02: Proceedings of the 2002 international workshop on System-level interconnect prediction
                April 2002
                116 pages
                ISBN:1581134819
                DOI:10.1145/505348

                Copyright © 2002 ACM

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                New York, NY, United States

                Publication History

                • Published: 6 April 2002

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