2002 Proceeding- General Chair:
- Jeff A. Davis,
- Program Chair:
- Dennis Sylvester
It is well-known that complex integrated wire systems consisting of signal, power, and clock distribution will place significant limits on performance, power dissipation, design complexity, and manufacturing cost of billion transistor systems. It is the assumption of this workshop that sophisticated system-level models for wire connectivity, demand, noise, and delay are needed to predict and optimize computer architectures, physical designs, and implementation technologies in order to maintain the exponential improvements in integration density, clock frequency, and cost per function as projected by the International Technology Roadmap for Semiconductor (ITRS).Wiring systems of complex digital circuits have certain collective properties that can be predicted with a minimal set of parameters. An engineer at IBM in the 1960's took only a few weeks to catalog data and observe that a power law relationship exists between the number of input/output pins and the number of basic circuit elements in digital systems. These rentian properties of netlists have been investigated and extended over the past thirty years -- presentations at this workshop reveal the latest discoveries for both rentian and non-rentian properties of complex wiring systems.Due to non-localized inductive coupling in multilevel wiring stacks, the collective electromagnetic properties of signal, power, and clock distribution must, in part, be considered at the system-level. The complex behavior of signal transients in IC wiring systems is exacerbated by the lack of smooth ground planes in a multilevel wiring stack and the emergence of multi-gigahertz clock frequencies. Part of the agenda of this workshop is to provide physical insight into the impact that inductance will have on multilevel wire systems over the next fifteen years.Primary applications of SLIP theory include early architectural planning, advanced interconnect timing analysis, FPGA architecture design, synthetic benchmark circuit generation, advanced placement and routing congestion metrics, a priori multilevel wire sizing and repeater insertion estimation, enhanced technology roadmap planning (e.g. low k-dielectrics, 3-D integration, integrated photonics, etc.), and early yield analysis. Over the years, system level simulators such as SUSPENS (Stanford), RIPE (RPI), BACPAC (Berkeley), GENESYS (Georgia Tech), and GTX (UCLA), have been developed to help estimate clock frequency, IPC, dynamic and static power dissipation, die size, number of required metal levels, and yield estimates for future VLSI systems. This year the workshop will discuss opportunities to enhance cycle time estimation, wire net length models, noise distribution predictions, and multilevel wiring network design, which are at the core of these comprehensive simulators.The program committee has chosen the content of SLIP2002 to provide a workshop with both tutorial information and cutting edge research in system-level interconnect prediction. We feel that this two day workshop will provide an exciting forum to help advance the field of system-level interconnect prediction so that its applications to the design of billion transistor systems can be rapidly developed.
Terminal optimization analysis for functional block re-use
The re-use of functional blocks within a large system on a chip (SoC) design results in a design trade-off between local intra-block and global inter-block communication. This paper develops a mathematical model to analyze the wire length distributions ...
Getting more out of Donath's hierarchical model for interconnect prediction
Though it has become one of the most popular techniques for a priori wirelength estimation, Donath's method is heavily constrained by the underlying circuit and architecture models. In this paper, we propose analytical and numerical extensions to this ...
Optimized pin assignment for lower routing congestion after floorplanning phase
A technique for the early estimation of congestion after the floorplanning phase is proposed in this paper, based on which an optimized pin assignment algorithm is implemented, aiming at reducing the routing congestion. Experiments show that the ...
FPGA interconnect planning
We present an FPGA interconnect planning methodology based on the empirical measure known as Rent's Rule[8]. We show that allocation of wire segment lengths during the FPGA architecture planning phase can be improved by taking into account interconnect ...
The X architecture: not your father's diagonal wiring
The X Architecture is an integrated-circuit wiring architecture based on the pervasive use of diagonal wires. Compared with the traditional, currently ubiquitous, Manhattan architecture, the X Architecture demonstrates a wire length reduction of more ...
Estimation needs for future networking systems interconnect
Architectures for new products in the networking systems space will make tradeoffs in many dimensions, including density, cost, performance (functionality, throughput, latency, etc.) and power. This paper describes metrics for system-level interconnects ...
Scaling trends of on-chip Power distribution noise
The design of power distribution networks in high performance integrated circuits has become significantly more challenging with recent advances in process technology. As on-chip currents exceed tens of amperes and circuit clock periods are reduced well ...
Technology trends in power-grid-induced noise
With technology scaling, the trend for high performance integrated circuits is towards higher power dissipation, higher operating frequency and lower power supply voltages. This causes a dramatic increase in power supply current being delivered through ...
Analytical signal integrity verification models for inductance-dominant multi-coupled VLSI interconnects
Novel signal integrity verification models for inductance-dominant RLC interconnect lines are developed by using a traveling-wave-based waveform approximation (TWA) technique. The multi-coupled line responses are decoupled into the eigenmodes of the ...
Reconfigurable interconnect for next generation systems
This paper describes our vision on the architectures required to build next generation systems. Next generation systems will not be PC centric anymore, but they will be built based on distributed, networked, power constraint embedded systems on a chip (...
Early probabilistic noise estimation for capacitively coupled interconnects
One of the critical challenges in today's high performance IC design is to take noise into account as early as possible in the design cycle. Current noise analysis tools [1, 7} are effective at analyzing and identifying noise in the post-route design ...
Refined single trunk tree: a rectilinear steiner tree generator for interconnect prediction
We devised an efficient and accurate estimation of the rectilinear Steiner minimal tree (SMT), which is an essential building block for on-line and posteriori interconnect prediction. We proposed a new rectilinear Steiner tree generator, Refined Single ...
Stochastic wire length sampling for cycle time estimation
Cycle time models perform an a-priori calculation of local signal delays by estimating the lengths of wires connecting different levels of synchronously clocked logic elements. Typically, a signal will have to pass through approximately 15-25 layers of ...
Wire layer geometry optimization using stochastic wire sampling
The variation of in-plane interconnect geometry (pitch and width) as a function of wiring level results in improved system level performance because the properties of each wiring layer may be tailored to the characteristic lengths of the wires allocated ...
Interconnect exploration for future wire dominated technologies
Storage "takes the centre stage" [4] in more and more information oriented systems because of the eternal push for more complex applications with especially larger and more complicated data types. In addition, the access speed, size and power ...
Recommendations
Acceptance Rates
| Year | Submitted | Accepted | Rate |
|---|---|---|---|
| SLIP '18 | 8 | 6 | 75% |
| Overall | 8 | 6 | 75% |