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Effect of node size on the performance of cache-conscious B+-trees

Published:10 June 2003Publication History

ABSTRACT

In main-memory databases, the number of processor cache misses has a critical impact on the performance of the system. Cache-conscious indices are designed to improve performance by reducing the number of processor cache misses that are incurred during a search operation. Conventional wisdom suggests that the index's node size should be equal to the cache line size in order to minimize the number of cache misses and improve performance. As we show in this paper, this design choice ignores additional effects, such as the number of instructions executed and the number of TLB misses, which play a significant role in determining the overall performance. To capture the impact of node size on the performance of a cache-conscious B+ tree (CSB+-tree), we first develop an analytical model based on the fundamental components of the search process. This model is then validated with an actual implementation, demonstrating that the model is accurate. Both the analytical model and experiments confirm that using node sizes much larger than the cache line size can result in better search performance for the CSB+-tree.

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          • Published in

            cover image ACM Conferences
            SIGMETRICS '03: Proceedings of the 2003 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
            June 2003
            338 pages
            ISBN:1581136641
            DOI:10.1145/781027
            • cover image ACM SIGMETRICS Performance Evaluation Review
              ACM SIGMETRICS Performance Evaluation Review  Volume 31, Issue 1
              June 2003
              325 pages
              ISSN:0163-5999
              DOI:10.1145/885651
              Issue’s Table of Contents

            Copyright © 2003 ACM

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            • Published: 10 June 2003

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            SIGMETRICS '03 Paper Acceptance Rate26of222submissions,12%Overall Acceptance Rate459of2,691submissions,17%

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