Nir Magen
Uri Weiser
ABSTRACT
Interconnect power is dynamic power dissipation due to switching of interconnection capacitances. This paper describes the characterization of interconnect power in a state-of-the-art high-performance microprocessor designed for power efficiency. The analysis showed that interconnect power is over 50% of the dynamic power. Over 90% of the interconnect power is consumed by only 10% of the interconnections. Relations of interconnect power to wire length distribution and hierarchy level of nets were examined. In light of the results, a router's algorithms were modified, to use larger wire spacing and minimal length routing for the high power consuming interconnects. The power-aware router algorithm was tested on synthesized blocks, demonstrating average saving of 14% in the dynamic power consumption without timing degradation or area increase. The results demonstrate the obtainable benefits of tuning physical design algorithms to save power.
- Borkar, S. Y. Design Challenges of Technology Scaling, IEEE MICRO, Jul./Aug. 1999, Vol. 19, No. 4, 23--29. Google Scholar
Digital Library
- Chatterjee, A., Nandakumar, M., and Chen, I.C. An Investigation of the Impact of Technology Scaling on Power Wasted as Short-Circuit Current in Low Voltage Static CMOS Circuits. in International Symposium on Low Power Electronic Design, 1996, 145--150. Google ScholarDigital Library
- Meindl, J. D., Davis, J. A., Zarkesh-Ha, P., Patel, C. S., Martin, K. P., and Kohl, P. A. Interconnect Opportunities for Gigascale Integration. IBM J. Res. & Dev., vol. 46, Mar/May 2002, 245--263. Google ScholarDigital Library
- Rabaey, J., Chandrakasan, A., and Nikolic, B. Digital Integrated Circuits: Second Edition. Prentice Hall, 2002.Google Scholar
- Liu, D., Svensson, C. Trading Speed for Low Power by Choice of Supply and Threshold Voltages. IEEE Journal of Solid-State Circuits, Vol. 28, No. 1, Jan. 1993.Google Scholar
- Pering, T., Burd, T., and Brodersen, R. The Simulation and Evaluation of Dynamic Voltage Scaling Algorithms. in Proceedings of the 1998 International Symposium on Low Power Electronics and Design, Aug. 1998, 76--81. Google ScholarDigital Library
- Berkelaar, M.R.C.M., and Jess, J.A.G. Gate Sizing in MOS Digital Circuits with Linear Programming. in Proceedings of the European Design Automation Conference, Mar. 1990, 12--15. Google ScholarDigital Library
- Farrahi, A.H., Chen, C., Srivastava, A., Tellez, G., and Sarrafzadeh, M. Activity-Driven Clock Design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, No. 6, Jun. 2001. Google ScholarDigital Library
- Genossar, D., and Shamir, N., Intel® Pentium® M Processor Power Estimation, Budgeting, Optimization, and Validation. Intel Technology Journal, Vol. 07, Iss. 02, May 2003, 43--50.Google Scholar
- Arunachalam, R., Rajagopal, K., and Pileggi, L.T. TACO: Timing Analysis with Coupling. in Proceedings of the Design Automation Conference, Jun. 2000, 266--269. Google ScholarDigital Library
- Stroobandt, D., Van Campenhout, J. Accurate Interconnection Length Estimations for Predictions Early in the Design Cycle. VLSI Design, Vol. 10 (1), 1999, 1--20.Google Scholar
- Davis, J., De, V.K., and Meindl, J. A Stochastic Wire-Length Distribution for Gigascale Integration (GSI) -- Part I: Derivation and Validation. IEEE Transaction on Electron Devices, Vol. 45, No. 3, Mar. 1998, 580--589.Google ScholarCross Ref
- Dally, W. J., and Lacy, S., VLSI Architecture: Past, Present, and Future. in Proceedings of the Advanced Research in VLSI conference, Atlanta, GA, 1999. Google ScholarDigital Library
- Horowitz, M., Ho, R., and Mai, K. The future of wires. in Proceedings of the IEEE, Vol. 89, no. 4, Apr. 2001.Google Scholar
- Ronen, R., Mendelson, A., Lai, K., Lu, S-L., Pollack, F., Shen, J.P. Coming Challenges in Microarchitecture and Architecture. Proceedings of the IEEE, Vol. 89, No. 3, Mar. 2001.Google Scholar
- International Technology Roadmap for Semiconductors (2001 Edition). Available: http://public.itrs.net/Files/2001ITRS/Home.htmGoogle Scholar
- Chern, J.H., Huang, J., Arledge, L., Li, P.C., and Yang, P. Multilevel Metal Capacitance Models for CAD Design Synthesis Systems. IEEE Electron Device Letters, vol. 13, Jan. 1992, 32--34.Google Scholar
- Cong, J., He, L., Koh C.K., and Madden, P. Performance Optimization of VLSI Interconnect Layout. Integration, the VLSI Journal, Vol. 21, Nov. 1996, 1--94. Google ScholarDigital Library
- Lee, Y.-M., Lai, H.Y., Chen, C.C.-P. Optimal Spacing and Capacitance Padding for General Clock Structures. in Proceedings of the conference on Asia South Pacific Design Automation Conference, Jan. 2001, 115--119. Google ScholarDigital Library
- Dees, W.A., and Smith, R.J. Performance of Interconnection Rip-Up and Reroute Strategies. in Proceedings of the 18th Design Automation Conference, Jun. 1981, 382--390. Google ScholarDigital Library
Index Terms
- Interconnect-power dissipation in a microprocessor
Recommendations
Leveraging Unused Cache Block Words to Reduce Power in CMP Interconnect
Power is of paramount importance in modern computer system design. In particular, the cache interconnect in future CMP designs is projected to consume up to half of the system power for cache fills and spills. Despite the power consumed by spills and ...
Wire topology optimization for low power CMOS
An increasing fraction of dynamic power consumption can be attributed to switched interconnect capacitances. Non-uniform wire spacing depending on activity had shown promising power reductions for on-chip buses. In this paper, a new and fast routing ...
Timing-aware power-optimal ordering of signals
A computationally efficient technique for reducing interconnect active power in VLSI systems is presented. Power reduction is accomplished by simultaneous wire spacing and net ordering, such that cross-capacitances between wires are optimally shared. ...
Reviews
Parthasarathi Dasgupta
This paper discusses the important issue of power dissipation in the design of high-performance microprocessors. Its major focus is on dynamic power consumption due to the switching of capacitors, and on the role of the interconnect power in this. The authors performed interconnect power analysis on a state-of-the-art microprocessor, made up of 77 million transistors in 130nm technology. The analysis was based on a stochastic dynamic power estimation method. For the purpose of the analysis, the authors considered the signal interconnect lengths between the drivers and receivers, but did not include the global clock grid. However, the capacitances included all types of capacitive loads, including the diffusion capacitances of the drivers, capacitances of the metal wiring, and the gate load of the receivers. Repeater gate and diffusion capacitances were also added to the original net. Metal capacitances included cross-capacitances between the nets, with the unit miller coupling factor (MCF). The results of the analysis indicate that interconnect switching accounts for about half of the total dynamic power consumption. The net topologies were split into two parts, namely, local and global nets. The local net was typically observed to have 30 percent higher fan out, and about 80 percent smaller interconnect capacitance, compared to the global net. However, as observed in the paper, the interconnect power was divided almost equally between the local and the global nets, due to the larger number of local nets. Ninety percent of the dynamic power was consumed by ten percent of the nets, and power reduction for these nets thus appeared to be the most demanding. The authors end by suggesting some methods to implement power-aware routing. One vital suggestion was to reduce capacitances, possibly via interconnect length reduction, and via increased spacing between routing wires. As a possible extension of an existing industrial router, based on rip-up and reroute, some of the nets were classified as power-critical nets, and rip-up of these nets was of the lowest priority. Some potential future work is also discussed. Online Computing Reviews Service
Access critical reviews of Computing literature here
Become a reviewer for Computing Reviews.
Comments