ABSTRACT
Timing analysis of concurrent programs running on multi-core platforms is currently an important problem. The key to solving this problem is to accurately model the timing effects of shared resources in multi-cores, namely shared cache and bus. In this paper, we provide an integrated timing analysis framework that captures timing effects of both shared cache and shared bus. We also develop a cycle-accurate simulation infra-structure to evaluate the precision of our analysis. Experimental results from a large fragment of an in-orbit spacecraft software show that our analysis produces around 20% over-estimation over simulation results.
- S. Baldawa and R. Sangireddy. CMP-SIM: an environment for simulating chip multiprocessor (cmp) architectures. http://www.utdallas.edu/~rama.sangireddy/CMP-SIM.Google Scholar
- T. Austin, E. Larson, and D. Ernst. Simplescalar: An infrastructure for computer system modeling. Computer, 2002. Google ScholarDigital Library
- European Space Agency. DEBIE -- First standard space debris monitoring instrument, 2008. Available at: http://gate.etamax.de/edid/publicaccess/debie1.php.Google Scholar
- ARM. ARM Cortex-A9 MPCore processor. http://www.arm.com/pdfs/ARMCortexA-9Processors.pdf.Google Scholar
- G. Varghese et al. Penryn: 45-nm next generation Intel core-2 processor. In IEEE Asian Solid-State Circuits Conf., 2007.Google Scholar
- S. Tam Rusu et al. A 65-nm Dual-Core Multithreaded Xeon processor with 16-MB L3 Cache. IEEE Journal Of Solid State Circuits, (1), 2007.Google Scholar
- D. Hardy and I. Puaut. WCET analysis of multi-level non-inclusive set-associative instruction caches. In RTSS, 2008. Google ScholarDigital Library
- H. Theiling, C. Ferdinand, and R. Wilhelm. Fast and precise wcet prediction by separated cache and path analyses. Real-Time Systems, 18:157--179, 2000. Google ScholarDigital Library
- Y. Li et al. Timing analysis of concurrent programs running on shared cache multi cores. In RTSS, 2009. Google ScholarDigital Library
- WCET benchmarks. http://www.mrtc.mdh.se/projects/wcet/benchmarks.html.Google Scholar
- Intel. Intel Core-2 Duo Processor. http://www.intel.com/products/processor/core2duo/index.htm.Google Scholar
- C.-G. Lee et al. Analysis of cache-related preemption delay in fixed-priority preemptive scheduling. IEEE Transactions on Computers, 47(6):700--713, 1998. Google ScholarDigital Library
- H. S. Negi, T. Mitra, and A. Roychoudhury. Accurate estimation of cache-related preemption delay. In CODES-ISSS, 2003. Google ScholarDigital Library
- S. Schliecker et al. Reliable performance analysis of a multicore multithreaded system-on-chip. In CODES-ISSS, 2008. Google ScholarDigital Library
- J. W. Lee and K. Asanovic. METERG: Measurement-based end-to-end performance estimation technique in QoS-capable multiprocessors. In RTAS, 2006. Google ScholarDigital Library
- J. Yan and W. Zhang. WCET analysis for multi-core processors with shared L2 instruction caches. In RTAS, 2008. Google ScholarDigital Library
- D. Hardy, T. Piquet, and I. Puaut. Using bypass to tighten WCET estimates for multi-core processors with shared instruction caches. In RTSS, 2009. Google ScholarDigital Library
- H. Kopetz. Real-time Systems Design Principles for Distributed Embedded Applications. Kluwer, 1999. Google ScholarDigital Library
- K. Tindell and J. Clark. Holistic schedulability for distributed hard real-time systems. Microprocessing & Microprogramming, 50(2--3), 1994. Google ScholarDigital Library
- J. Rosen et al. Bus access optimization for predictable implementation of real-time applications on multiprocessor systems-on-chip. In RTSS, 2007. Google ScholarDigital Library
- M. Paolieri et al. Hardware support for WCET analysis of hard real-time multicore systems. In ISCA, 2009. Google ScholarDigital Library
Index Terms
- Modeling shared cache and bus in multi-cores for timing analysis
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