Joseph Sloan
ABSTRACT
Much recent research [8, 6, 7] suggests significant power and energy benefits of relaxing correctness constraints in future processors. Such processors with relaxed constraints have often been referred to as stochastic processors [10, 15, 11]. In this paper we present three approaches for building applications for such processors. The first approach relies on relaxing the correctness of the application based upon an analysis of application characteristics. The second approach relies upon detecting and then correcting faults within the application as they arise. The third approach transforms applications into more error tolerant forms. In this paper, we show how these techniques that enhance or exploit the error tolerance of applications can yield significant power and energy benefits when computed on stochastic processors.
- M. Carbin, D. Kim, S. Misailovic, and M. C. Rinard, editors. the 33rd ACM SIGPLAN Conference on Programming Language Design and Implementation(PLDI), Beijing. ACM, 2012. Google Scholar
Digital Library
- Timothy A. Davis. University of florida sparse matrix collection. NA Digest, 92, 1994.Google Scholar
- W. Fung, I. Sham, G. Yuan, and T. Aamodt. Dynamic warp formation and scheduling for efficient gpu control flow. In MICRO, pages 407--420, 2007. Google ScholarDigital Library
- R. Hegde and N. R. Shanbhag. Energy-efficient signal processing via algorithmic noise-tolerance. In Low Power Electronics and Design, 1999. Proceedings. 1999 International Symposium on, pages 30--35, 1999. Google ScholarDigital Library
- Kuang-Hua Huang and J. A. Abraham. Algorithm-based fault tolerance for matrix operations. Computers, IEEE Transactions on, C-33(6):518--528, 1984. Google ScholarDigital Library
- A. Kahng, S. Kang, R. Kumar, and J. Sartori. Designing a processor from the ground up to allow voltage/reliability tradeoffs. In IEEE International Symposium on High-Performance Computer Architecture(HPCA), 2010.Google ScholarCross Ref
- A. Kahng, S. Kang, R. Kumar, and J. Sartori. Recovery-driven design: A methodology for power minimization for error tolerant processor modules. In the 47th Design Automation Conference (DAC), June 2010. Google ScholarDigital Library
- A. Kahng, S. Kang, R. Kumar, and J. Sartori. Slack redistribution for graceful degradation under voltage overscaling. In Asia and South Pacific Design and Automation Conference (ASPDAC), January 2010. Google ScholarDigital Library
- D. Kesler, B. Deka, and R. Kumar. A hardware acceleration technique for gradient descent and conjugate gradient. In Application Specific Processors (SASP), 2011 IEEE 9th Symposium on, june 2011. Google ScholarDigital Library
- R. Kumar. Stochastic processors. In NSF Workshop on Science of Power Management, March 2009.Google Scholar
- S. Narayanan, J. Sartori, R. Kumar, and D. L. Jones. Scalable stochastic processors. In Design, Automation Test in Europe Conference Exhibition (DATE), 2010. Google ScholarDigital Library
- A Nemirovski, A Juditsky, G Lan, and A Shapiro. Robust stochastic approximation approach to stochastic programming. SIAM Journal on Optimization, 19(4), 2009. Google ScholarDigital Library
- J. Sartori and R. Kumar. Architecting processors to allow voltage/reliability tradeoffs. In CASES, 2011. Google ScholarDigital Library
- J. Sartori and R. Kumar. Compiling for energy efficiency on timing speculative processors. In the 49th Design Automation Conference(DAC), June 2012. Google ScholarDigital Library
- N. Shanbhag, R. Abdallah amd R. Kumar, and D. Jones. Stochastic computation. In the 47th Design Automation Conference(DAC), June 2010. Google ScholarDigital Library
- J. Sloan, D. Kesler, R. Kumar, and A. Rahimi. A numerical optimization-based methodology for application robustification: Transforming applications for error tolerance. In Dependable Systems and Networks (DSN), 2010, June 2010.Google ScholarCross Ref
- J. Sloan, R. Kumar, G. Bronevetsky, and T. Kolev. Algorithmic approaches to low overhead fault detection for sparse linear algebra. In Dependable Systems and Networks (DSN), 2012, 2012-july 1 2012. Google ScholarDigital Library
- Wikipedia. Mandelbrot set, 2011. http://en.wikipedia.org/wiki/Mandelbrot_set.Google Scholar
Index Terms
- On software design for stochastic processors
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