ABSTRACT
Existing literature documents a number of techniques for combining a set of independent datapath designs into a single datapath that is run-time configurable to the functionality of any datapath in the set. This paper explores how delay, energy and area overhead attributable to reconfigurability scales with the number of configurable functionalities, independent of the design of specific datapaths. Distinct design space regions are identified based upon common scaling properties, with implications on the design and feasible efficiency bounds of reconfigurable devices.
- K. Atasu, C. Ozturan, G. Dundar, O. Mencer, and W. Luk. CHIPS: Custom hardware instruction processor synthesis. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 27(3):528, 2008. Google ScholarDigital Library
- R. Battiti and M. Protasi. Reactive local search for the maximum clique problem. Technical report, Algorithmica, 2001.Google Scholar
- L. Bertrand and E. Casseau. Automated multimode system design for high performance DSP applications. In Proceedings of the 17th European Signal Processing Conference (EUSIPCO 2009), pages 1289--1293, 2009.Google Scholar
- C. Chavet, C. Andriamisaina, P. Coussy, E. Casseau, E. Juin, P. Urard, and E. Martin. A design flow dedicated to multi-mode architectures for DSP applications. In Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, pages 604--611. IEEE Press, 2007. Google ScholarDigital Library
- L.-y. Chiou, S. Bhunia, and K. Roy. Synthesis of application-specific highly efficient multi-mode cores for embedded systems. ACM Trans. Embed. Comput. Syst., 4(1):168--188, 2005. Google ScholarDigital Library
- P. Christie and D. Stroobandt. The interpretation and application of Rent's rule. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 8(6):639--648, Dec 2000. Google ScholarDigital Library
- K. Compton. Architecture Generation of Customized Reconfigurable Hardware. PhD thesis, Northwestern University, 2003. Google ScholarDigital Library
- K. Compton and S. Hauck. Totem: Custom reconfigurable array generation. IEEE Symposium on FPGAs for Custom Computing Machines, 2001. Google ScholarDigital Library
- A. Correale, Jr. Overview of the power minimization techniques employed in the ibm powerpc 4xx embedded controllers. ISLPED '95, pages 75--80, 1995. Google ScholarDigital Library
- D. Cronquist, C. Fisher, M. Figueroa, P. Franklin, and C. Ebeling. Architecture design of reconfigurable pipelined datapaths. 20th Anniversary Conference on Advanced Research in VLSI, 1999., pages 23--40, 1999. Google ScholarDigital Library
- J. Davis, V. De, and J. Meindl. A stochastic wire-length distribution for gigascale integration (GSI)-Part I: Derivation and validation. IEEE Transactions on Electron Devices, 45(3), 1998.Google Scholar
- J. Davis, V. De, and J. Meindl. A stochastic wire-length distribution for gigascale integration (GSI)-Part II: Applications to clock frequency, power dissipation, and chip size estimation. IEEE Transactions on Electron Devices, 45(3), 1998.Google Scholar
- W. Donath. Placement and average interconnection lengths of computer logic. Circuits and Systems, IEEE Transactions on, 26(4):272--277, Apr 1979.Google Scholar
- W. Donath. Wire length distribution for placements of computer logic. IBM Journal of Research and Development, 25(2-3):152--155, 1981. Google ScholarDigital Library
- W. Geurts, F. Catthoor, S. Vernalde, and H. De Man. Accelerator Data-Path Synthesis for High-Throughput Signal Processing Applications. Kluwer Academic Pub, 1997. Google ScholarDigital Library
- S. Hauck, K. Compton, K. Eguro, M. Holland, S. Phillips, and A. Sharma. Totem: Domain-Specific Reconfigurable Logic. submitted to IEEE Transactions on VLSI, 2008.Google Scholar
- Z. Huang and S. Malik. Managing dynamic reconfiguration overhead in systems-on-a-chip design using reconfigurable datapaths and optimized interconnection networks. Design, Automation and Test in Europe Conference, 0:0735, 2001. Google ScholarDigital Library
- I. Kuon and J. Rose. Measuring the gap between FPGAs and ASICs. In FPGA '06: Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays, pages 21--30, New York, NY, USA, 2006. ACM Press. Google ScholarDigital Library
- P. Kwan and C. T. Clarke. FPGAs for improved energy efficiency in processor based systems. Advances in Computer Systems Architecture: 10th Asia-Pacific Conference, ACSAC 2005, Singapore, October 24--26, 2005: Proceedings, 2005. Google ScholarDigital Library
- B. Landman and R. Russo. On a pin versus block relationship for partitions of logic graphs. IEEE Transactions on Computers, C-20:1469--1479, December 1971. Google ScholarDigital Library
- S. Malik. Analysis of cyclic combinational circuits. In IEEE/ACM International Conference on Computer-Aided Design, pages 618--625, Nov 1993. Google ScholarDigital Library
- N. Moreano, G. Araujo, Z. Huang, and S. Malik. Datapath merging and interconnection sharing for reconfigurable architectures. In ISSS '02: Proceedings of the 15th international symposium on System Synthesis, pages 38--43, 2002. Google ScholarDigital Library
- N. Moreano, E. Borin, C. D. Souza, and G. Araujo. Efficient datapath merging for partially reconfigurable architectures. In IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, pages 969--980, 2005. Google ScholarDigital Library
- K. Parnell and R. Bryner. Comparing and contrasting FPGA and microprocessor system design and development. Technical report, Xilinx, 2004.Google Scholar
- M. Rullmann and R. Merker. Maximum edge matching for reconfigurable computing. In Reconfigurable Architectures Workshop at 13th IEEE International Parallel & Distributed Processing Symposium (IPDPS 2006), Rhodes, Greece. Citeseer, 2006. Google ScholarDigital Library
- M. Rullmann, R. Merker, H. Hinkelmann, P. Zipf, and M. Glesner. An Integrated Tool Flow to Realize Runtime-Reconfigurable Applications on a New Class of Partial Multi-Context FPGAs. In Proc. 19th Intl. Conf. on Field Programmable Logic and Appls., 2009.Google ScholarCross Ref
- N. Shirazi, W. Luk, and P. Cheung. Automating production of run-time reconfigurable designs. Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 0:147, 1998. Google ScholarDigital Library
- C. C. d. Souza, A. M. Lima, G. Araujo, and N. B. Moreano. The datapath merging problem in reconfigurable systems: Complexity, dual bounds and heuristic evaluation. J. Exp. Algorithmics, 2005. Google ScholarDigital Library
- D. Stroobandt. Improving Donath's technique for estimating the average interconnection length in computer logic. ELIS Technical Report, 1996.Google Scholar
- M. Zuluaga and N. Topham. Resource sharing in custom instruction set extensions. In Proceedings of the 6th IEEE Symposium on Application Specific Processors. (Jun. 2008), 2008. Google ScholarDigital Library
Index Terms
- On the asymptotic costs of multiplexer-based reconfigurability
Recommendations
An evolvable hardware system in Xilinx Virtex II Pro FPGA
In this paper, a new circuit architecture for image filter evolution is proposed. The evolvable system is based on the implementation of a search algorithm in the PowerPC processor which is available in Xilinx Virtex II Pro Field Programmable Gate ...
DRAF: a low-power DRAM-based reconfigurable acceleration fabric
ISCA'16FPGAs are a popular target for application-specific accelerators because they lead to a good balance between flexibility and energy efficiency. However, FPGA lookup tables introduce significant area and power overheads, making it difficult to use FPGA ...
DRAF: a low-power DRAM-based reconfigurable acceleration fabric
ISCA '16: Proceedings of the 43rd International Symposium on Computer ArchitectureFPGAs are a popular target for application-specific accelerators because they lead to a good balance between flexibility and energy efficiency. However, FPGA lookup tables introduce significant area and power overheads, making it difficult to use FPGA ...
Comments