ABSTRACT
This paper demonstrates a first-order, linear power estimation model ha uses performance counters to estimate run-time CPU and memory power consumption of the Intel PXA255 processor. Our model uses a set of power weights that map hardware performance counter values to processor and memory power consumption. Power weights are derived offline once per processor voltage and frequency configuration using parameter estimation echniques. They can be applied in a dynamic voltage/frequency scaling environment by setting six descriptive parameters. We have tested our model using a wide selection of benchmarks including SPEC2000, Java CDC and Java CLDC programming environments. The accuracy is quite good; average estimated power consumption is within 4% of he measured average CPU power consumption. We believe such power estimation schemes can serve as a foundation for intelligent, power-aware embedded systems tha dynamically adapt to the device's power consumption
- E. Duesterwald, C. Cascaval, S. Dwarkadas, Characterizing and Predicting Program Behavior and its Variability Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques (PACT'03) October 2003. Google ScholarDigital Library
- P. Nagpurkar and C. Krintz, Visualization and Analysis of Phased Behavior in Java Programs. ACM International Conference on the Principles and Practice of Programming in Java (PPPJ) June 2004. Google ScholarDigital Library
- C. Isci and M. Martonosi, Runtime Power Monitoring using High-End Processors: Methodology and Empirical Data, 2003. MICRO'36. Google ScholarDigital Library
- P. F. Sweeney et al., Using Hardware Performance Monitors to Understand the Behavior of Java Applications. USENIX 3rd Virtual Machine Research and Technology Symposium (VM'04) May, 2004. Google ScholarDigital Library
- A. S. Dhodapkar and J. E. Smith, Managing Multi-Configuration Hardware via Dynamic Working Set Analysis Proceedings of the 29th annual International Symposium on Computer Architecture (ISCA'02) May 2002. Google ScholarDigital Library
- Intel XScale Microarchitecture for the PXA255 Processor: User's Manual Intel Corporation, March 2003. Order No. 278796.Google Scholar
- SPEC JVM98 Benchmarks, Standard Performance Evaluation Corporation. http://www.spec.org/osg/jvm98/.Google Scholar
- Ulrik Pagh Schultz et al. Compiling Java for Low-end Embedded Systems. Language, Compiler and Tool Support for Embedded Systems (LCTES'03) June 2003. Google ScholarDigital Library
- W. Shiue and C. Chakrabarti, Memory Exploration for Low Power, Embedded Systems. Proceedings of the 36th ACM/IEEE conference on Design automation 1999. Google ScholarDigital Library
- F. Bellosa, The Benefits of Event-Driven Energy Accounting in Power-Sensitive Systems Proceedings of the 9th workshop on ACM SIGOPS European workshop 2002. Google ScholarDigital Library
- R. Joseph and M. Martonosi, Run-time Power Estimation in High Performance Microprocessors Proceedings of the 2001 international symposium on Low power electronics and Design (ISLPED'01) 2001. Google ScholarDigital Library
- Intel Corp, Intel Pentium 4 and Intel Xeon Processor Opt. Ref. Man., 2002. developer.intel.com/design/Pentium4/manuals/248966.htm.Google Scholar
- I. Kadayif, T Chinoda, M. Kandemir, N. Vijaykrishnan, M. J. Irwin and A. Sivasubramaniam, vEC: Virtual Energy Counters. Proceedings of the 2001 ACM SIGPLAN-SIGSOFT workshop on Program analysis for software tools and engineering. 2001. Google ScholarDigital Library
- T. Li and L. Kurian John, Run-time Modeling and Estimation of Operating System Power Consumption. ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems 2003. Google ScholarDigital Library
- Intel DBPXA255 Development Platform for the Intel Personal Internet Client Architecture, Intel Corporation, February 2003. Order No. 278701-001.Google Scholar
- M. R. Guthaus et al. MiBench: A free, Commercially Representative Embedded Benchmark Suite. July 2001. IEEE 4th Annual Workshop on Workload Characterization. Google ScholarDigital Library
- G. Contreras, M. Martonosi, J. Peng, R. Ju and G. Lueh, XTREM: A Power Simulator for the Intel XScale Core. The 2004 Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'04) June 2004. Google ScholarDigital Library
Index Terms
- Power prediction for intel XScale® processors using performance monitoring unit events
Recommendations
XTREM: a power simulator for the Intel XScale® core
LCTES '04: Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systemsManaging power concerns in icroprocessors has become a pressing research problem across the domains of computer architecture, CAD, and compilers. As a result, several parameterized cycle-level power simulators have been introduced. While these ...
XTREM: a power simulator for the Intel XScale® core
LCTES '04Managing power concerns in icroprocessors has become a pressing research problem across the domains of computer architecture, CAD, and compilers. As a result, several parameterized cycle-level power simulators have been introduced. While these ...
The XTREM power and performance simulator for the Intel XScale core: Design and experiences
Managing power concerns in microprocessors has become a pressing research problem across the domains of computer architecture, CAD, and compilers. As a result, several parameterized cycle-level power simulators have been introduced. While these ...
Comments