Top

Published in:

2024 | OriginalPaper | Chapter

A 0.94 V Dynamic Bias Double Tail Comparator for High-Speed Applications in 5 nm Technology

Authors : Valentina Marazzi, Enrico Monaco, Claudio Nani, Danilo Manstretta

Published in: Applications in Electronics Pervading Industry, Environment and Society

Publisher: Springer Nature Switzerland

Activate our intelligent search to find suitable subject content or patents.

search-config

AI-assisted search

Off

Abstract

The necessity of efficient comparators in modern ADCs calls for new two-stages topologies that overcome the Strongarm limitations in terms of common-mode offset and gain dependency. The latest fashion is represented by dynamic bias integrators coupled with low power and low noise latches. The dynamic bias significantly reduces the overall power consumption, a feature which the second stage has to maintain; also, a CMOS implementation is usually adopted to gain more robustness. Starting from the comparator with dynamic floating inverter amplifier [1], a new structure has been derived and explained. The architecture has been simulated in 5 nm FinFET technology and compared to the state-of-the-art for very stringent power, noise and speed targets. Nonetheless, the proposed topology matches various applications thanks to its multiple degrees of freedom which allow the designer plenty of room for further improvements. The continuously scaling technology will favour this CMOS dynamic bias implementation even more.

Dont have a licence yet? Then find out more about our products and how to get one now:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

über 102.000 Bücher
über 537 Zeitschriften

aus folgenden Fachgebieten:

Automobil + Motoren
Bauwesen + Immobilien
Business IT + Informatik
Elektrotechnik + Elektronik
Energie + Nachhaltigkeit
Finance + Banking
Management + Führung
Marketing + Vertrieb
Maschinenbau + Werkstoffe
Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

inform now

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

über 67.000 Bücher
über 390 Zeitschriften

aus folgenden Fachgebieten:

Automobil + Motoren
Bauwesen + Immobilien
Business IT + Informatik
Elektrotechnik + Elektronik
Energie + Nachhaltigkeit
Maschinenbau + Werkstoffe

Jetzt Wissensvorsprung sichern!

inform now

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

über 67.000 Bücher
über 340 Zeitschriften

aus folgenden Fachgebieten:

Bauwesen + Immobilien
Business IT + Informatik
Finance + Banking
Management + Führung
Marketing + Vertrieb
Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

inform now

previous chapter Speeding Up Non-archimedean Numerical Computations Using AVX-512 SIMD Instructions

next chapter A RISC-V Hardware Accelerator for Q-Learning Algorithm

Tang X et al (2020) An energy-efficient comparator with dynamic floating inverter amplifier. IEEE J Solid-State Circ 55(4):1011–1022. https://doi.org/10.1109/JSSC.2019.2960485CrossRef

Pisati M et al (2020) A 243-mW 1.25–56-Gb/s continuous range PAM-4 42.5-dB IL ADC/DAC-based transceiver in 7-nm FinFET. IEEE J Solid-State Circ 55(1):6–18. https://doi.org/10.1109/JSSC.2019.2936307CrossRef

Li S, et al (2020) Low power SAR ADC design with digital background calibration algorithm. Symmetry 12(11):1757. https://doi.org/10.3390/sym12111757

Kull L, et al (2013) A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32 nm digital SOI CMOS. In: 2013 IEEE international solid-state circuits conference digest of technical papers, San Francisco, CA, USA, pp 468–469. https://doi.org/10.1109/ISSCC.2013.6487818

Bindra HS et al (2022) A 174μVRMS input noise, 1 GS/s comparator in 22nm FDSOI with a dynamic-bias preamplifier using tail charge pump and capacitive neutralization across the latch. IEEE Int Solid-State Circ Conf (ISSCC) 2022:1–3. https://doi.org/10.1109/ISSCC42614.2022.9731728CrossRef

Shang E, et al (2020) The factors that influence the effective mobility in 5 NM PMOS Finfet design. In: 2020 China semiconductor technology international conference (CSTIC), Shanghai, China, pp 1–3. https://doi.org/10.1109/CSTIC49141.2020.9282475

Bindra HS et al (2018) A 1.2-V dynamic bias latch-type comparator in 65-nm CMOS with 0.4-mV input noise. IEEE J Solid-State Circ 53(7):1902–1912. https://doi.org/10.1109/JSSC.2018.2820147CrossRef

Kobayashi T, et al (1992) A current-mode latch sense amplifier and a static power saving input buffer for low-power architecture. In: 1992 symposium on VLSI circuits digest of technical papers, Seattle, WA, USA, pp 28–29. https://doi.org/10.1109/VLSIC.1992.229252

van Elzakker M et al (2010) A 10-bit charge-redistribution ADC consuming 1.9 μW at 1 MS/s. IEEE J Solid-State Circ 45(5):1007–1015. https://doi.org/10.1109/JSSC.2010.2043893CrossRef

Title: A 0.94 V Dynamic Bias Double Tail Comparator for High-Speed Applications in 5 nm Technology
Authors: Valentina Marazzi
Enrico Monaco
Claudio Nani
Danilo Manstretta
Publisher: Springer Nature Switzerland
Book: Applications in Electronics Pervading Industry, Environment and Society
Print ISBN: 978-3-031-48120-8

Electronic ISBN: 978-3-031-48121-5

Copyright Year: 2024
DOI: https://doi.org/10.1007/978-3-031-48121-5_10

Springer Professional

Abstract

Please log in to get access to your license.

Dont have a licence yet? Then find out more about our products and how to get one now:

Springer Professional "Wirtschaft+Technik"

Springer Professional "Technik"

Springer Professional "Wirtschaft"