A 10T Subthreshold SRAM Cell with Minimal Bitline Switching for Ultra-Low Power Applications

High noise margins and low power dissipation are the major attributes of the SRAM cells used in ultra-low power applications. This paper proposes a 10T Static Random-Access memory (SRAM) with data aware dynamic feedback control and disturb free read which enhances the noise margins in the sub-threshold region. Exploiting the dynamic threshold MOS transistors (DTMOS) technique reduces the read access time of the proposed memory cell. As this cell offers single ended write operation with the bitlines kept at logic HIGH which leads to large saving in dynamic power due to charging/discharging operation on bitlines. Therefore, proposed SRAM reduces the activity factor of discharging the bitlines for each write pattern. The simulation has been carried out in 65 nm technology node to show the comparison among the existing techniques and proposed cell. The proposed memory cell has write static noise margin (WSNM) of 1.7x and 1.48x compared to iso-area 6T and Schmitt Trigger based (ST2) SRAM cells respectively at supply voltage of 300 mV. Read operation is data controlled which improves the read margin. Dynamic threshold technique increases read current for faster read operation. Read SNM is 2x, 1.16x and 1.4x of iso-area 6T, differential data aware 9T and Schmitt trigger SRAM (ST2) respectively. These features enable the cell for ultralow power applications.