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Design and Application for Sealing of Strengthening Computer for Anti-hard Environment Read chapter Read first chapter

2019 | OriginalPaper | Chapter

A 12.5-Gb/s Equalizer with CTLE and a 4-Tap Quarter-Rate DFE in 40 nm Technology

Authors : Qing Xu, Jianjun Chen, Yueyue Chen, Bin Liang, Bo Xiong, Yuan Luo, Jizuo Zhang

Published in: Computer Engineering and Technology

Publisher: Springer Singapore

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Abstract

On account of finite channel bandwidth and reflection, receiver cannot receive data accurately resulting from ISI. To satisfy the transmission requirements of PCIE3.1 and Rapid IO3.2, this paper presents a 12.5 Gb/s equalizer based on 40 nm CMOS. It uses Continuous-Time Linear Equalizer (CTLE) and a quarter-baud-rate decision feedback equalizer (DFE) with 4 taps. Finally, the receiver can effectively balance data and restore eye diagram with a channel loss of 28 dB at 12.5 Gb/s. The layout area of equalizer is 0.66 mm2, and its consumption is 33.08 mW from a 1.1-V supply.

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Metadata
Title
A 12.5-Gb/s Equalizer with CTLE and a 4-Tap Quarter-Rate DFE in 40 nm Technology
Authors
Qing Xu
Jianjun Chen
Yueyue Chen
Bin Liang
Bo Xiong
Yuan Luo
Jizuo Zhang
Copyright Year
2019
Publisher
Springer Singapore
Book
Computer Engineering and Technology

Print ISBN: 978-981-13-5918-7

Electronic ISBN: 978-981-13-5919-4

Copyright Year: 2019

DOI
https://doi.org/10.1007/978-981-13-5919-4_10