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2015 | OriginalPaper | Chapter

7. A Zero-Crossing Algorithm-Based Digital Phase-Locked Loop

Authors : Basab Bijoy Purkayastha, Kandarpa Kumar Sarma

Published in: A Digital Phase Locked Loop based Signal and Symbol Recovery System for Wireless Channel

Publisher: Springer India

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Abstract

The structure of a Digital Phase-Locked Loop (DPLL)-based systems for dealing with Nakagami-m fading is proposed in this chapter. The emphasis of the work is the implementation of the essential components of a DPLL for better reception of signals with certain modulation transmitted through Nakagami-m channels. A sixth order polynomial fitting algorithm for better phase-frequency detection has been implemented, which has helped to attain optimum performance of DPLL. The results of simulation of the proposed DPLL with Nakagami-m fading and QPSK modulation shows that the proposed method provides better performance than existing systems of similar type.

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previous chapter Synchronization
next chapter Least Square Polynomial Fitting-Based Digital Phase-Locked Loop
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Metadata
Title
A Zero-Crossing Algorithm-Based Digital Phase-Locked Loop
Authors
Basab Bijoy Purkayastha
Kandarpa Kumar Sarma
Copyright Year
2015
Publisher
Springer India
Book
A Digital Phase Locked Loop based Signal and Symbol Recovery System for Wireless Channel

Print ISBN: 978-81-322-2040-4

Electronic ISBN: 978-81-322-2041-1

Copyright Year: 2015

DOI
https://doi.org/10.1007/978-81-322-2041-1_7