Adaptable Embedded Systems

Conflicting trends can be observed in the hardware industry for embedded systems, which are presently being required to run several different applications with distinctive behaviors, becoming more heterogeneous. At the same time, users also demand these systems to operate during an extended period of time, creating extra pressure for energy efficiency. While transistor size shrinks, processors are getting more sensitive to fabrication defects, aging and soft faults, which increase the costs associated with their production. To make this situation even worse, in most of the time designers are stuck with the need to sustain binary compatibility, in order to support the huge amount of embedded software already deployed.In this challenging context, adaptability in multiple levels is the key for sustaining the aforementioned requirements. Embedded systems must adapt themselves to better execute their applications with the lowest possible power dissipation, while respecting their original functional behavior and their set of non-functional constraints (such as maximum execution time or power budget). They also must adapt when scheduling these different applications to be executed on their distinct hardware components, depending on availability, performance requirements and energy budget; or still adapt themselves to keep working when a defect comes from the fabrication process, or when a fault appears at runtime. High resilience allows increased yield and reduced costs, even with aggressive scaling or by the use of unreliable technologies or operation in harsh environments.This chapter overviews the toughest challenges that embedded software and hardware engineers face when designing new devices and systems, and how these systems are expected to grow in complexity in the forthcoming years. In the end of this chapter it will become clear how only aggressive adaptability can tackle these conflicting design constraints in a sustainable fashion, and still allow huge fabrication volumes. Each challenge is developed in details throughout the next chapters, providing an extensive literature review as well as settling a promising research agenda for adaptability.

Embedded systems have been going through a transition process. Some years ago, they were dedicated and built to run very specific applications. Nowadays, they must be prepared to support a large range of different applications unforeseen at design time, with stringent performance and energy requirements. Therefore, the use of specific hardware components to deal with such applications is mandatory. In this scenario, besides profiling the behavior of these applications so it is possible to figure out what are their limits of performance improvements, we evaluate the efficiency of generic hardware accelerators considering different grains of optimization. In addition, we show the impact of the operating system code in the overall execution time in modern embedded systems. Finally, with the assistance of an analytical model, we study the trade off in exploiting instruction and thread level parallelism when area, energy and performance are taken into account.

This chapter aims to explain the basics of reconfigurable systems. It starts with a basic explanation on how these architectures work, their main principles, and where the gains come from. After that, this chapter gives an overview on the classification of reconfigurable systems, which includes granularity, instruction types and coupling. Following this discussion, several and different examples of architectures that have been used both in the academy and in the industry are shown. They are presented according to the classification studied in the previous sections of this same chapter. Finally, a brief overview on recent dataflow machines is given, as their structure is very similar to some of the reviewed reconfigurable systems.

Over the past years, the growing performance gap between large memories and computational logic fueled an increased usage of complex memory hierarchies. The main goal of such hierarchies is to provide data and instructions to the processing elements with maximum efficiency, both in terms of latency and energy consumption. The importance of using an efficient memory hierarchy places it as a critical component also in embedded systems, where one often faces strict performance and power constraints.In Chap.2, we have discussed that, since different applications have different requirements and behaviors, the optimal processing structure for each one is also different. This same property applies when one considers memories: a memory hierarchy specifically tailored for a given use pattern is able to provide optimum throughput with reduced energy consumption. This same specific structure, however, may perform poorly when used directly with other applications, without any adaptation. Hence, just as reconfigurable architectures adapt themselves to better fit each application, reconfigurable memories should shape to the requirements of the application under execution. In this chapter we present the basic concepts and technology tradeoffs involved in memory hierarchies and discuss possible approaches to provide adaptability for such structures.

Network-on-Chip, usually referred as NoC, has replaced the common bus due to its scalability and reliability in the multi and many core scenarios. Therefore, in this chapter, we discuss how a NoC may adapt to provide the best response to the different requirements of nowadays heterogeneous applications running on complex System-on-Chips. We discuss adaptability in the NoC by considering three different levels: protocol, architecture and link levels. For each of them, there are specific adaptive techniques that have been proposed to improve performance, reliability, yield and/or reduce power and energy consumption.

As has been emphasized throughout this book, it is necessary a high level of adaptability to cope with the high heterogeneous behavior of recent applications. At the same time, binary code compatibility is mandatory, so the large amount of already existing software can be reused without any kind of modification. In this scenario, this chapter discusses dynamic optimization techniques, how they can be used to improve performance, how they maintain binary compatibility and some case studies. The chapter starts presenting Binary translation. Its main concepts are clarified, as well as the main challenges that a binary translator mechanism must handle to work properly. The section ends with a detailed view of some examples of Binary Translation machines. Then, Reuse is discussed, and diverse types of it are covered: instruction reuse, value prediction, basic block, trace reuse and dynamic trace memoization. Furthermore, according to the discussion made in Chap.3, even though reconfigurable systems present huge potentials in terms of performance and energy, they alone cannot deal with the high heterogeneous behavior of recent applications neither maintain binary compatibility. Therefore, this chapter ends presenting approaches that use reconfigurable architectures together with mechanisms that somehow reassembles the behavior of the dynamic optimization techniques.

The continued scaling of current CMOS technology has brought new challenges in device’s fabrication and maintenance. As the feature sizes approach their physical limits, the circuit becomes more prone to faults. For this reason, as the circuits scale to deep-submicron world, including a fault tolerance approach in all devices becomes mandatory. In this chapter, we will show that, besides all the advantages adaptability presents, it can also be a very powerful mechanism to provide fault tolerance to future devices and increase yield and reliability. Chapter5 already discussed some details about using adaptability in Network on Chips targeted to fault tolerance. We continue this discussion by presenting some of the main works on fault tolerance using adaptability, aiming to provide to the reader enough information to understand why and how adaptability is used in this context. This chapter is divided in four primary sections. The first section introduces the reader to fault tolerance and the problems in working with deep-submicron scale. Section7.2 presents the general concepts and terminology used in fault tolerance field and an overview of fault tolerance techniques. Hardware, software, time and information redundancy methods are considered. In Sect.7.3, we discuss some fault tolerance strategies in traditional architectures, multicore systems and reconfigurable architectures. Finally, in Sect.7.4, we present the conclusions on this topic and discuss some open problems.

Instruction level parallelism exploitation has become extremely costly in terms of power and area, bringing insignificant performance gains, if one considers the last generation of processors. Therefore, multiprocessing systems appear as an alternative to push up performance of current embedded devices by exploiting parallelism at a different level. There is a wide range of characteristics to be considered when designing a multiprocessing system, and this chapter focuses on discussing this huge design space. First, the state-of-the-art of multiprocessing systems in both academic and market fields are shown. Then, adaptability is discussed, since it is getting more and more relevant in such environments. Finally, we discuss some issues that surround the multiprocessing scenario, such as the communication mechanisms and programming models.

Adaptability requires the software to change based on the several states that the adaptive hardware can assume, and, hence, current main stream programming languages, compilers, and runtime systems will not be enough to support software development for adaptive systems. We discuss techniques that could be used to support a changing environment, requirements and hardware resources in order to make the adaptive hardware platform a programmable device. The objective of this chapter is to discuss and present the challenges that a changing hardware platform imposes to software design, and to point a research agenda for adaptive software. Furthermore, this chapter presents a novel hardware/software framework that could foster new ideas and future research on adaptive systems.

Systems will have to change and evolve. Different trends can be observed in the embedded systems industry, for its products are presently being required to run several different applications with distinct behaviors, becoming even more heterogeneous, with extra pressure on power and energy consumption.Furthermore, while transistor size shrinks, processors are becoming more sensitive to manufacturing defects, aging and soft faults, increasing the costs associated with their production. To make this situation even worse, designers are stuck with the need to sustain binary compatibility, in order to support the huge amount of software already deployed.