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2018 | OriginalPaper | Chapter

Adaptive Access Path Selection for Hardware-Accelerated DRAM Loads

Authors : Markus Dreseler, Timo Gasda, Jan Kossmann, Matthias Uflacker, Hasso Plattner

Published in: Databases Theory and Applications

Publisher: Springer International Publishing

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Abstract

For modern main memory database systems, the memory bus is the main bottleneck. Specialized hardware components of large NUMA systems, such as HPE’s GRU, make it possible to offload memory transfers. In some cases, this improves the throughput by 30%, but other scenarios suffer from reduced performance. We show which factors influence this tradeoff. Based on our experiments, we present an adaptive prediction model that supports the DBMS in deciding whether to utilize these components. In addition, we evaluate non-coherent memory access as an additional access method and discuss its benefits and shortcomings.

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Footnotes
1
All benchmarks were executed on an SGI UV 300H with 6 TB RAM and eight Intel E7-8890 v2 processors. Our code was compiled with gcc 7.2 at https://static-content.springer.com/image/chp%3A10.1007%2F978-3-319-92013-9_1/464772_1_En_1_IEq2_HTML.gif .
 
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Metadata
Title
Adaptive Access Path Selection for Hardware-Accelerated DRAM Loads
Authors
Markus Dreseler
Timo Gasda
Jan Kossmann
Matthias Uflacker
Hasso Plattner
Copyright Year
2018
Book
Databases Theory and Applications

Print ISBN: 978-3-319-92012-2

Electronic ISBN: 978-3-319-92013-9

Copyright Year: 2018

DOI
https://doi.org/10.1007/978-3-319-92013-9_1

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