Advertisement
Published in:
2012 | OriginalPaper | Chapter
Advances in Parallel Transistor-Level Circuit Simulation
Authors : Heidi K. Thornquist, Eric R. Keiter
Published in: Scientific Computing in Electrical Engineering SCEE 2010
Publisher: Springer Berlin Heidelberg
Activate our intelligent search to find suitable subject content or patents.
Select sections of text to find matching patents with Artificial Intelligence. powered by
Select sections of text to find additional relevant content using AI-assisted search. powered by
Parallel transistor-level circuit simulation has the potential to significantly impact the need for reliably determining parasitic effects for modern feature sizes. Incorporating parallelism into a simulator at both coarse and fine-grained levels, through the use of message-passing and threading paradigms, is supported by the advent of inexpensive clusters, as well as multi-core technology. However, its effectiveness is reliant upon the development of efficient parallel algorithms for traditional “true SPICE” circuit simulation. In this paper, we will discuss recent advances in fully parallel transistor-level full-chip circuit simulation, concluding with scaling results from a newer strategy for the parallel preconditioned iterative solution of circuit matrices.