Advances in VLSI and Embedded Systems

A phase-lock loop (PLL) is an elementary component for many electronic applications. The phase detector (PD) and phase frequency detector (PFD) are the major components used in designing PLL. This paper presents a novel PD and PFD circuit designed using dynamic CMOS architecture. A thorough step by step examination of PD and PFD design is carried out in this work. The proposed circuit optimizes the channel length, aspect ratio and supply voltage for improved performance of the designed circuit in terms of power, speed, and power delay products (PDP). Results obtained with 16 nm channel length are better compared to 22, and 32 nm. Proper validation of the results obtained are presented and the supply voltages are monitored between 0.6 and 1.4 V. Aspect ratio (width to length ratios) is varied in the range of 1–5. Tanner T-Spice tool is used for simulation. Compared with the several techniques proposed before, the presented circuit gives the best tradeoff to choose between different channel lengths according to user requirements.

A modular reduction unit is a primary element of Residue Number Systems and cryptography implementations. The modular reduction unit is required to perform cryptographic algorithms such as Elliptical Curve Cryptography (ECC) and Digital Signature Algorithms (DSA). The operation of modular reduction unit is utilized in various modular arithmetic such as modular addition, modular multiplication, and division. In this paper, three binary adders are developed using Switching Activity (SA). The proposed binary adder is designed using the logic decomposition method. Based on the presented full adders, the Modular Reduction Unit (MRU) is enhanced. Three MRUs are simulated and synthesized using Xilinx Viva-do Zynq-7000 device. From the synthesis results, the proposed modular reduction unit is improved in terms of total cell count and dynamic power consumption by (56% and 46%) over the conventional and modified conventional methods. Power Delay Product and Energy delay Product of the proposed MRU is enhanced by (~56%, ~ 44%) over the conventional and modified conventional methods.

Recent advances in the field of RF front end design have replaced multiple narrowband Low-Noise Amplifiers (LNA) with one wideband LNA to support a variety of bands and standards. The effectiveness of the RF front end is heavily dependent on the performance of the LNA, as it is the first block in the RF receiver. High gain, high linearity, low noise figure, and low power dissipation are all desirable characteristics in an LNA. Because of the wideband LNA’s large bandwidth, a lot of interference gets in without being filtered, and if the LNA isn’t linear, it causes harmonic distortion, cross modulation, intermodulation, as well as a drop in 1dB compression point (P1dB) and sensitivity. To reduce the negative effects of intermodulation, wideband LNA linearization requires improvements in both second-order intercept point (IIIP2) and third-order intercept point (IIP3). In this paper, previously reported linearization techniques that improve both IIP2 and IIP3 are investigated thoroughly and divided into five main categories: (a) feedback, (b) feedforward, (c) complementary derivative superposition (CDS), (d) noise/distortion cancellation, and e) post distortion. After extensive analysis, it has been found that noise/distortion cancellation and complementary derivative superposition (CDS) have the potential to deliver reliable wideband linearization. Furthermore, rather than using a single linearization technique, integrating many strategies can result in improved linearization.

A 9T SRAM cell with low power and high speed that works in the ultra-low-power supply is presented. This SRAM is the modified structure of single ended 8T SRAM by connecting word line and one nMOS with high width in the bottom of the twisted connected inverter pair. This work illustrates a 9T SRAM cell that dissipates low power and has high speed during read time and write time. This SRAM cell is a little modification of the SE8T SRAM cell, in which one of the ends of the cell is used to write the information and the other is used to read the information written on the cell. In the same cell, one nMOS transistor has been added to provide better read access time. This stacking of the transistor provides the cell a better path to discharge the bit lines.

In this paper Schmitt trigger based three different static random access memory bit cells–7, 9 and 10 T–are designed at a 32 nm technology node and their results are analyzed. The static noise margin obtained for 7, 9, and 10 T SRAM bit cells for hold operation are–22, 131, and 126 mV respectively. While, for the read operation the noise margin values are–22, 131, and 27 mV respectively. The dynamic write analysis reveals that the 9 T SRAM cell has a minimal pulse width requirement of 35 ns for a successful write operation. These cache memories are subject to temperature variation operation. Therefore, the Schmitt trigger based bit cells are analyzed by varying temperatures from −10 to 110 ℃. The temperature variation analysis demonstrates 10 T SRAM cell has the least variation in static performance. Another parameter used to compare the performance of the cells is leakage current. This identifies 9 T SRAM bit cell has the maximum leakage current with 635 pA and 630 pA for Q = ‘0’ and ‘1’ respectively.

This paper proposes an approximate 8-bit multiplier design using an approximate 4:2 compressor. This paper proposes a new approach to designing the approximate compressor. The proposed approach reduces the switching activity, thereby reduces the dynamic power. The proposed compressor is 78.33% energy efficient than the existing ones. The proposed approximate multiplier is used in image processing application to demonstrate the output visual quality of image versus approximate hardware.

Approximate computing allows substantial power saving at the cost of curtailed accuracy. The inaccurate outputs are tolerated by applications such as image and multimedia processing, data mining, etc. due to their inherent error tolerance. Multipliers are the most prominent circuits which are required for deploying these applications on digital processors. In this paper, a power-efficient unsigned multiplier is designed that uses a novel approximate 4–2 compressor. Simulation results demonstrate that the proposed multipliers have 11.07\(\%\) reduction in energy compared to exact multiplier and provide a high PSNR in the range of 20.47 to 35.23 dB for image multiplication application.

This paper presents a novel active inductor-based low noise amplifier (LNA), which is capable of achieving high gain and low noise figure (NF) in a small die area. The proposed design consists of two stages. The first part comprises a modified cascode stage containing dual common source transistors. The authors replaced the passive drain inductor with an active inductor to make the circuit area-efficient. The second part consists of a feed-forward path (FFP), which boosts the gain and reduces the NF of the modified cascode stage. The post-layout simulations of the 2.4 GHz LNA in 180 nm CMOS technology, using cadence virtuoso, demonstrate the performance improvement in terms of gain, NF and area. The NF, power gain and IIP3 of the amplifier are 0.402 dB, 14.11 dB and -13.45 dBm, respectively. The power consumption is 5.63 mW from a 1.8 V power supply. The area of the core is 0.002 mm\(^2\). The FFP enhances the gain by 12.2% and reduces the NF by 7.2% compared to the modified cascode LNA. The figure-of-merit shows that the designed amplifier is around two times better than the previously reported ones.

This paper presents a fully on-chip tunable impedance matching scheme to reduce the power transfer losses across the antenna rectifier interface in an RF energy harvesting system. The proposed matching scheme avoids bulky off-chip inductors and utilizes on-chip varactor-based inductors for low form-factor applications. The proposed scheme has been designed and simulated using a 0.18 \(\mathrm \mu \)m CMOS technology node for an operating frequency of 953 MHz. A study of the \(S_{11}\) characteristics exhibits a magnitude of greater than −20 dB, thereby illustrating the effectiveness of the proposed matching scheme.

This work proposes designing and simulation of fault tolerance and diagnosis mechanism for ALU units as an integral part of advanced CPUs. ALU units are the most important and core component of the processor. In the application where the system is under harsh environmental conditions, it is most important to design a fault-tolerant and reliable processor for the proper continuity of operation on the field. We have demonstrated the combined technique of fault tolerance and diagnosis mechanism to help the processor to improve performance. The proposed design is able to identify the faulty module and generate an exception when the fault counter reaches some user-defined threshold. This proposed design is implemented in Verilog code using Quartus II 64-bit Version 13.0.1 Build 232 06/122013 SJ Web Edition software tool. The waveforms of the proposed design are simulated using ModelSim ALTERA STARTER EDITION 10.1d Revision: 2012.11. Simulation has been done under all possible fault cases for the considered module and as a result, the system will be able to go into a fail-safe and diagnosis state as per the proposed technique. It is capable of identifying faulty modules in case of external environment effect on result/system.

Interferometry is an important diagnostic technique for plasma electron density measurement in tokamaks. The measured line integrated electron density is directly related to the phase difference between the reference and transmitted paths. There are several phase detection techniques, e.g., Fast Fourier Transform, CORDIC, ArcTAN, Zero-cross, and cross-correlation which are used for phase measurement. Calibration of the developed interferometer is required for actual electron density estimation. Calibration requires path length variation between transmitting and receiving antennas. Variation in the distance between antennas is directly related to the phase change of the interferometer. An Arduino-based pneumatic calibrator is designed and developed for interferometer calibration. The developed heterodyne interferometer using I-Q demodulator has been calibrated using the pneumatic calibrator in the laboratory. Calibration has been done using single and multiple path length displacements. The displacement variation is recorded using an ultrasonic sensor (HC-SR04). The developed calibrator has 2–10 cm distance range with 0.3 cm range accuracy. The developed calibrator will be used in diagnostic calibration for the interferometer, reflectometer, etc.

The rapid development of artificial intelligence and mobile computation facilitates the life of the blind and visually impaired people. One of the main issues, the visually impaired face, is the inability to realize the event's happenings in their surroundings. In recent years, Computer Vision and Deep Learning have received extensive coverage. Visual object tracking is one of the key areas of computer vision. The main purpose of visual object tracking from streaming video frames is to detect or connect target objects. YOLO, an approach used for object detection, follows regression to spatially separate bounding boxes and associate class probabilities. This approach has gained a lot of popularity lately. Unlike models like R-CNN, that require thousands of neural networks, for YOLO, one neural network is sufficient enough to predict all the bounding boxes and their class probabilities from the entire image in just one evaluation. Since the entire pipeline is just one network, optimization can be done easily on the detection performance. The YOLO model has various versions like YOLOv2, YOLOv3, YOLOv4 and YOLO9000. It outperforms other detection methods when generalizing natural images from other domains like artwork. YOLOv3 with proper Hyperparameter Tuning can also overcome the Speed-Accuracy Trade-off. In this paper, use of these models on a common image proves that YOLOv3 can identify 15.15% more objects with a 33% faster response time. This paper has information about the application of YOLOv3 model with hyper-parameter tuning to aid the visually impaired people by virtually visualizing events occurring in their surroundings.

Agriculture has always remained as an integral part of the world. As the human population keeps on rising, the demand for food also increases and so is the dependency on the agriculture industry. But in today’s scenario because of low yield, less rainfall, etc., a dearth of manpower is created in this agricultural sector and people are moving to live in the cities, and villages are becoming more and more urbanized. On the other hand, the field of robotics has seen tremendous development in the past few years. The concepts like Deep Learning (DL), Artificial Intelligence (AI), Machine Learning (ML) are being incorporated with robotics to create autonomous systems for various sectors like automotive, agriculture, assembly line management, etc. Deploying such autonomous systems in the agricultural sector helps in many aspects like reducing manpower, better yield, and nutritional quality of crops. So, in this paper, the system design of an autonomous agricultural robot that primarily focuses on weed detection is described. A modified deep learning model for the purpose of weed detection is also proposed. The primary objective of this robot is the detection of weed on a real-time basis without any human involvement but it can also be extended to design robots in various other applications involved in farming like weed removal, plowing, harvesting, etc. in turn making farming industry more efficient. The source code and other paper-related documents can be found at https://​github.​com/​Dhruv2012/​Autonomous-Farm-Robot

Coronavirus is the most challenging threat today in our society. This virus has caused a huge number of deaths worldwide. Experts are still searching for an effective and long-term vaccine. In the present scenario, people are relying on wearing mask, self-quarantine, social-distancing and sanitizing hands for defending this infectious coronavirus. The health-care units, academicians, researchers and governments as well as business houses are trying their level best to prevent the spread of this disease. In this paper, design and implementation of an Internet of Things (IoT)-based smart and cost-effective system for tracking and monitoring of COVID-19 suspected patients have been introduced. Proposed system has significant social impact as it can be used to reduce the chances of community transmission of this deadly virus. Proposed reusable cost-effective system can help the hospital and local authority to monitor and track the movement of quarantined people.

In this paper, the ambipolarity property of Silicon Tunnel Field Effect Transistor (TFET) is utilized to sense transitions in high bit rate (frequency) digital signals or Non-Return-to-Zero (NRZ), Manchester, differential Manchester and Bipolar data bits. This study is done using simulations run on Sentaurus (sdevice) TCAD with a resistive load Silicon Double Gate TFET inverter, with an output load capacitance \(C_{L}\) of 3 fF, 50 nm channel length (\(L_{G}\)) and 10 nm lateral distance between two gates (\(T_{si}\)). This study includes variations in the load resistance, rise/fall time of signal bits. The ambipolar TFET device is doped in such a manner that the device characteristics are the same for both gate to source voltages (\(\pm V_{gs}\)). The output from this inverter-based sensor is shown in the form of impulses, having information about rise/fall time due change in bit pattern. It has been observed that the maximum (\(V_{max})\) and minimum \((V_{min})\) output voltage spikes depend on the load resistance (\(R_{L}\)), linearly for lower values and deviates from linear behavior (quadratic function) for higher \(R_{L}\) values with constant rise and fall time . It is also found that \(V_{max}\) and \(V_{min}\) depend on the rise and fall times with constant \(R_{L}\) values as well. \(R_{L}\) range in this work is from 800 \(\Omega \) to 25 \(K\Omega \) with the rise/fall times range from 50 ps to 500 ps.

Process variation has been aroused as a prospective design concern in current nano-scale integrated circuits (ICs). With the shrink in technology size, graphene nano-ribbon has proven to be a potential futuristic material for on-chip interconnect system. This research paper addresses the stochastic parameter variability on novel on-chip interconnect system. The driver-interconnect-load (DIL) system is incorporated for variability analysis where driver and load are driven by CMOS inverter circuit, and interconnect is modeled by an equivalent distributed line model of multi-layer graphene nanoribbons (MLGNR) interconnects. The effect of variability is analyzed using the prospective techniques like parametric analysis, process corner, and Monte Carlo simulation. The signal integrity issues like propagation delay and power dissipation are accurately analyzed for MLGNR interconnects under process-induced variations using SPICE at 32 nm technology node. Furthermore, the effective time-domain analysis tool, eye diagram is investigated for the stated interconnect system model. Eye diagram is implemented on Advanced Design System (ADS) tool for the estimation of digital signal errors in time and power, respectively.

In this work, we intensively analyzed the performance of junctionless (JL) double-gate (DG) MOSFET for biosensing applications. The dielectric modulation technique has been to detect the biomolecules. Drain current sensitivity (ΔI_D) and threshold voltage sensitivity (ΔV_th) are taken as sensitivity metrics for biomolecule detection. It is observed that JL-DG-MOSFET gives a very good ΔI_D in the order of 10¹². Further, the impact of channel parameters like channel thickness (T_C) and channel length (L_C) on the sensitivity metrices has also been examined. It is found that downscaling of T_C and upscaling of L_C improves the threshold voltage sensitivity. However, we observed a peak at L_C = 150 nm for drain current sensitivity. Hence, a lower T_C (= 8 nm) and L_C (= 150 nm) results in better sensitivities and thus can be used for designing JL-DG-FET based biosensors.

In this paper, a 20 nm TFET-based temperature invariant Low Dropout (LDO) voltage regulator is presented. The comparative analysis is done with a 32 nm CMOS-based LDO regulator. The LDO regulator is implemented using an Error amplifier (EA) which is a TFET-based two-stage Op-Amp. The EA has a high open-loop DC gain of 66.8 dB and phase margin (PM) of 60.9\( ^{\circ } \). The Gain Bandwidth Product (GBW) of the EA is 1.44 GHz, 3 dB frequency of 708.12 kHz, and Gain Margin (GM) of 18.7 dB for load capacitance (\(C_{L} \)) of 100 fF and compensation capacitance (\(C_{C} \)) of 25 fF. The temperature variation analysis shows that only 500 \(\upmu \)V of change in the output voltage occurs for \( - \)50 to 100 \( ^{\circ } \)C temperature variation and only 400 \(\upmu \)V of change occurs in the output voltage for \(I_{LOAD} \) variation from 0 to 50 mA. The designed LDO voltage regulator working with a reference voltage of 0.72 V offers a PSRR 39.6 dB for frequency up to 210 kHz. The designed TFET-based LDO voltage regulator consumes 113.86 \(\upmu \)W of power.

Digital Microfluidics is rapidly evolving to automate procedures in biochemistry and molecular biology laboratories. Digital microfluidic biochip (DMFB) is a lab-on-chip (LOC) systems platform. DMFB technology offers abundant spatial parallelism and is inherently programmable based on micro-droplet manipulation on a miniaturized chip. DMFBs have evolved as an alternative to conventional biochemical laboratories. Droplets are transported, dispensed, analyzed, stored, reacted, or mixed on a platform with the help of insulated electrodes. DMFBs work with discrete droplet manipulation rather than continuous liquid flow. Several adjacent cells form a module that will carry out the required functionalities such as mixing, dilution, and detection. Module placement is an important task, and in this work, we formulate and solve the placement problem in DMFBs using a simple heuristic method. Modules should be placed according to the schedule inputted with minimum deviation and use as little area as possible to facilitate fault-tolerance. Two popular bioassays, multiplexed in vitro diagnostics and Colorimetric protein assay, are used for experimental evaluation.

Floorplan is one of the most critical steps of the physical design of VLSI Design flow. Decreasing size, interconnects, power consumption, and chip leakage are always on the top priority list for consumers and researchers. This article presents the latest advancements in one of the hot research topics in VLSI Physical Design: 3D Floorplanning. A lot of research articles have been studied for this article, and only major research points from some chosen relevant to 3D architecture articles have been incorporated in this paper. The 3D VLSI floorplan field is quite vast than the 2D VLSI floorplan and is comparatively less explored. This article reviews various aspects of floorplanning that cover floorplanning based on volume, tiers, vias, TSVs, and other representations of 3D VLSI Floorplan. These techniques, when applied as algorithms, help in simplifying the problem. These algorithms help optimize results that increase the chip’s overall performance. Some of the central representations have been incorporated in Sect. 5. Conclusion with research gap and future scope is described in the end.

The electrical breakdown of oxides and oxide/semiconductor interfaces is one of the major reasons for failure of CMOS ICs, especially when they are exposed to high stress conditions like the space environment and high energy laboratory, etc. To mitigate radiation effects and the circuit failures thereof, Triple Modular Redundancy (TMR) and shielding are used at circuit and system levels which is costlier and puts burden on the system. This work recommends novel radiation sensor for minimizing radiation effects. Main objective of this work is to design a radiation sensor to overcome the degradation effects due to radiation. As 180 nm is considered as best node for space technology, this work aims at designing sensor for this node. The proposed system would be tested for effects of Gamma-ray and 10 KeV X-rays. Sensor parameters are fixed based on the mathematical and simulation results. Using Cogenda TCAD capacitor sensor is simulated having Silicon as substrate martial with Na doping of 1e\(^{16}\) cm\(^{-3}\) and Oxide thickness of 330 nm. Simulated and calculated threshold voltage is 3.9 V and 4.1 V respectively. Sensor tested with low and high radiation doses ranging from 100 rad to 10 Mrad. Threshold shift is considered as sensitivity parameter, sensitivity of sensor for 0–1 Mrad is 0.5 mV/krad.

In the floorplan representation of VLSI Design, B*-Tree and O-tree representations are recommended due to their vast advantages over other models. Out of this, B*-Tree representation is widely used due to its simplicity in implementation. But we may lack the significant benefits and flexibility that O-Tree representation offers in its execution. In this paper, a new method of O-tree implementation (Code-Based Location Search and position) is presented, which is relatively easy and flexible in use without any lag in performance. Also, this algorithm is implemented in the newly improved memetic algorithm. Experimental results are checked on standard MCNC benchmark circuits and compared with previous research. It has been found that the proposed algorithm is efficient in obtaining optimized floorplan area in lesser time. Performance metrics have improved to a great extent using this algorithm. Conclusion with results and discussions is drawn at the end.