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2018 | OriginalPaper | Chapter

7. Algorithms for the Basic Operations

Authors : Jean-Michel Muller, Nicolas Brunie, Florent de Dinechin, Claude-Pierre Jeannerod, Mioara Joldes, Vincent Lefèvre, Guillaume Melquiond, Nathalie Revol, Serge Torres

Published in: Handbook of Floating-Point Arithmetic

Publisher: Springer International Publishing

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Abstract

Among the many operations that the IEEE 754 standards specify (see Chapter 3), we will focus here and in the next two chapters on the five basic arithmetic operations: addition, subtraction, multiplication, division, and square root. We will also study the fused multiply-add (FMA) operator. We review here some of the known properties and algorithms used to implement each of those operators. Chapter 8 and Chapter 9 will detail some examples of actual implementations in, respectively, hardware and software.

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previous chapter Languages and Compilers
next chapter Hardware Implementation of Floating-Point Arithmetic
Footnotes
1
In many cases, there are better ways of implementing the operation.
 
2
In this discussion, we assume that 4. 999…9 ∞ is written 5. 0 ∞ ; otherwise, this sentence is not true. This remark is academic: a computer will only deal with finite representations, which do not raise this ambiguity.
 
3
When the input is + ∞, it is the exact result + ∞ which must be returned; see [267, §6.1].
 
4
We remind the reader that there remains some ambiguity in the standard, since underflow can be detected before or after rounding. See Sections 2.​1.​3 and 3.​1.​6.​4 for more on this. Here, we describe underflow detection before rounding.
 
Literature
[83]
N. Brunie, F. de Dinechin, and B. Dupont de Dinechin. A mixed-precision fused multiply and add. In 45th Asilomar Conference on Signals, Systems, and Computers, November 2011.
[84]
N. Brunie, F. de Dinechin, and B. Dupont de Dinechin. Mixed-precision merged multiplication and addition operator. Patent WO/2012/175828, December 2012.
[116]
M. Cornea, C. Anderson, J. Harrison, P. T. P. Tang, E. Schneider, and C. Tsen. A software implementation of the IEEE 754R decimal floating-point arithmetic using the binary encoding format. In 18th IEEE Symposium on Computer Arithmetic (ARITH-18), pages 29–37, June 2007.
[117]
M. Cornea, J. Harrison, C. Anderson, P. T. P. Tang, E. Schneider, and E. Gvozdev. A software implementation of the IEEE 754R decimal floating-point arithmetic using the binary encoding format. IEEE Transactions on Computers, 58(2):148–162, 2009.MathSciNetCrossRef
[118]
M. Cornea, J. Harrison, and P. T. P. Tang. Scientific Computing on Itanium ®; -based Systems. Intel Press, Hillsboro, OR, 2002.
[184]
L. Eisen, J. W. Ward, H. W. Tast, N. Mäding, J. Leenstra, S. M. Mueller, C. Jacobi, J. Preiss, E. M. Schwarz, and S. R. Carlough. IBM POWER6 accelerators: VMX and DFU. IBM Journal of Research and Development, 51(6):1–21, 2007.CrossRef
[186]
M. D. Ercegovac and T. Lang. Division and Square Root: Digit-Recurrence Algorithms and Implementations. Kluwer Academic Publishers, Boston, MA, 1994.MATH
[187]
M. D. Ercegovac and T. Lang. Digital Arithmetic. Morgan Kaufmann Publishers, San Francisco, CA, 2004.
[260]
E. Hokenek, R. K. Montoye, and P. W. Cook. Second-generation RISC floating point with multiply-add fused. IEEE Journal of Solid-State Circuits, 25(5):1207–1213, 1990.CrossRef
[267]
[269]
IEEE Computer Society. IEEE Standard for Floating-Point Arithmetic (revision of IEEE Std 754-2008). 2017.
[291]
C.-P. Jeannerod, H. Knochel, C. Monat, and G. Revy. Faster floating-point square root for integer processors. In IEEE Symposium on Industrial Embedded Systems (SIES’07), pages 324–327, 2007.
[292]
C.-P. Jeannerod, H. Knochel, C. Monat, and G. Revy. Computing floating-point square roots via bivariate polynomial evaluation. IEEE Transactions on Computers, 60(2):214–227, 2011.MathSciNetCrossRef
[293]
C.-P. Jeannerod, H. Knochel, C. Monat, G. Revy, and G. Villard. A new binary floating-point division algorithm and its software implementation on the ST231 processor. In 19th IEEE Symposium on Computer Arithmetic (ARITH-19), June 2009.
[359]
T. Lang and J. D. Bruguera. Floating-point multiply-add-fused with reduced latency. IEEE Transactions on Computers, 53(8):988–1003, 2004.CrossRef
[400]
D. Lutz and N. Burgess. Overcoming double-rounding errors under IEEE 754-2008 using software. In 44th Asilomar Conference on Signals, Systems, and Computers, pages 1399–1401, November 2010.
[406]
P. Markstein. IA-64 and Elementary Functions: Speed and Precision. Hewlett-Packard Professional Books. Prentice-Hall, Englewood Cliffs, NJ, 2000.
[424]
R. K. Montoye, E. Hokonek, and S. L. Runyan. Design of the IBM RISC System/6000 floating-point execution unit. IBM Journal of Research and Development, 34(1):59–70, 1990.CrossRef
[425]
P. Montuschi and P. M. Mezzalama. Survey of square rooting algorithms. Computers and Digital Techniques, IEE Proceedings E., 137(1):31–40, 1990.CrossRef
[467]
S. F. Oberman. Floating point division and square root algorithms and implementation in the AMD-K7 microprocessor. In 14th IEEE Symposium on Computer Arithmetic (ARITH-14), pages 106–115, April 1999.
[492]
J. A. Pineiro and J. D. Bruguera. High-speed double-precision computation of reciprocal, division, square root, and inverse square root. IEEE Transactions on Computers, 51(12):1377–1388, 2002.MathSciNetCrossRef
[501]
E. Quinnell, E. E. Swartzlander, and C. Lemonds. Floating-point fused multiply-add architectures. In 41st Asilomar Conference on Signals, Systems, and Computers, pages 331–337, November 2007.
[502]
[511]
J. E. Robertson. A new class of digital division methods. IRE Transactions on Electronic Computers, EC-7:218–222, 1958. Reprinted in [583].CrossRef
[533]
S. M. Rump, P. Zimmermann, S. Boldo, and G. Melquiond. Computing predecessor and successor in rounding to nearest. BIT Numerical Mathematics, 49(2):419–431, 2009.MathSciNetCrossRef
[550]
P.-M. Seidel. Multiple path IEEE floating-point fused multiply-add. In 46th International Midwest Symposium on Circuits and Systems, pages 1359–1362, 2003.
[602]
K. D. Tocher. Techniques of multiplication and division for automatic binary computers. Quarterly Journal of Mechanics and Applied Mathematics, 11(3):364–384, 1958.MathSciNetCrossRef
[613]
A. Vázquez. High-Performance Decimal Floating-Point Units. Ph.D. thesis, Universidade de Santiago de Compostela, 2009.
[629]
X. Wang, S. Braganza, and M. Leeser. Advanced components in the variable precision floating-point library. In Field-Programmable Custom Computing Machines, pages 249–258, 2006.
Metadata
Title
Algorithms for the Basic Operations
Authors
Jean-Michel Muller
Nicolas Brunie
Florent de Dinechin
Claude-Pierre Jeannerod
Mioara Joldes
Vincent Lefèvre
Guillaume Melquiond
Nathalie Revol
Serge Torres
Copyright Year
2018
Book
Handbook of Floating-Point Arithmetic

Print ISBN: 978-3-319-76525-9

Electronic ISBN: 978-3-319-76526-6

Copyright Year: 2018

DOI
https://doi.org/10.1007/978-3-319-76526-6_7

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