An Efficient Hardware Architecture for High Throughput AES Encryptor Using MUX Based Sub Pipelined S-Box

In this paper an efficient structural architecture is proposed for AES Encryption process to achieve high throughput with less device utilization. Breakable and controllable structures for main AES blocks at the gate level are designed and used here. The control unit using high speed combinational logic circuit is designed to control the AES structural architecture. Modified MUX based S-Box is introduced in AES instead of S-Box to reduce the area without affecting the throughput. In addition Encryption process Mix-columns transformation is modified to reduce the hardware complexity. The five stage subpipelining is introduced in AES MUX based S-Box with six pipelining stages in AES encryption process to increase throughput further. The aim of this work is to investigate both the existing and new architectures. The modified MUX based S-Box for Rijndael algorithm has been used in the 128-bit AES encryption process. The role of five stage sub-pipelined MUX based S-Box of 128-bit pipelined AES is to reduce the critical path delay to minimum for achieving high clock frequency. The rows of multiplexer in AES architecture were used for the breaking and controlling of the design. The modified 128-bit encryption was implemented on Virtex-4, Virtex-5, and Spartan 3 FPGA Devices. The results of the proposed architecture are analysed, throughput and area for the implemented design are calculated. The calculated results are compared with other architecture (Liberatori et al. in 3rd southern proceedings of the IEEE conference on programmable logic, SPL’07, pp 195–198, 2007; Farashahi et al. in Microelectron J 45:1014–1025, 2014; Good and Benaissa in IET Inf Secur 1(1):1–10, 2007; Sireesha and Madhava Rao in Int J Sci Res 3(9):1–5, 2013; Gielata et al. in Proceedings of the international conference on signals and electronic systems (ICSES), pp 137–140, 2008; El Adib and Raissouni in Int J Inf Netw Secur 1(2):1–10, 2012; Good and Benaissa in Lecture Notes Computer Science, vol 3659, pp 427–440, 2005). From the results it is obtained that the proposed architecture gives 58 % improvement with 1.08 % reduction in area.