Skip to main content
Top

2018 | OriginalPaper | Chapter

An Efficient Model for Soft Error Vulnerability of Dynamic Circuits

Authors : Yan Sun, Yuesheng Cao, Jinwen Li, Tiejun Li

Published in: Computer Engineering and Technology

Publisher: Springer Singapore

Activate our intelligent search to find suitable subject content or patents.

search-config
loading …

Abstract

Dynamic circuits are widely used in high-speed circuit. However, dynamic circuits are very vulnerable to soft errors. An analytical model of critical charge for vulnerable nodes of dynamic circuits is developed. As the accurate model is too complex to calculate, a simplified efficient model is proposed by using an approximate method. Proposed model are verified by SPICE simulation and error analysis respectively. Results demonstrate that these models have high accuracy and can be used both in the efficient analysis and automatic CAD tools.

Dont have a licence yet? Then find out more about our products and how to get one now:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 340 Zeitschriften

aus folgenden Fachgebieten:

  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Versicherung + Risiko




Jetzt Wissensvorsprung sichern!

Literature
1.
go back to reference Kumar, J., Tahoori, M.B.: A low power soft error suppression technique for dynamic logic. In: 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 454–462 (2005) Kumar, J., Tahoori, M.B.: A low power soft error suppression technique for dynamic logic. In: 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 454–462 (2005)
2.
go back to reference Cha, H., Patel, J.H.: A logic-level model for \(\alpha \)-particle hits in CMOS circuits. In: IEEE International Conference on Computer Design, pp. 538–542 (1993) Cha, H., Patel, J.H.: A logic-level model for \(\alpha \)-particle hits in CMOS circuits. In: IEEE International Conference on Computer Design, pp. 538–542 (1993)
3.
go back to reference Naseer, R., Draper, J., Boulghassoul, Y., Dasgupta, S., Witulski, A.: Critical charge and SET pulse widths for combinational logic in commercial 90 nm CMOS technology. In: ACM Great Lakes Symposium on VLSI, pp. 227–230 (2007) Naseer, R., Draper, J., Boulghassoul, Y., Dasgupta, S., Witulski, A.: Critical charge and SET pulse widths for combinational logic in commercial 90 nm CMOS technology. In: ACM Great Lakes Symposium on VLSI, pp. 227–230 (2007)
4.
go back to reference Rossi, D., Cazeaux, J.M., Omana, M., Metra, C., Chatterjee, A.: Accurate linear model for SET critical charge estimation. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 17, 1161–1166 (2009)CrossRef Rossi, D., Cazeaux, J.M., Omana, M., Metra, C., Chatterjee, A.: Accurate linear model for SET critical charge estimation. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 17, 1161–1166 (2009)CrossRef
5.
go back to reference Raji, M., Ghavami, B.: Soft error rate reduction of combinational circuits using gate sizing in the presence of process variations. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25, 247–260 (2017)CrossRef Raji, M., Ghavami, B.: Soft error rate reduction of combinational circuits using gate sizing in the presence of process variations. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25, 247–260 (2017)CrossRef
6.
go back to reference Shivakumar, P., Kistler, M., Keckler, S.W., Burger, D., Alvisi, L.: Modeling the effect of technology trends on the soft error rate of combinational logic. In: International Conference on Dependable Systems and Networks, pp. 389–398 (2002) Shivakumar, P., Kistler, M., Keckler, S.W., Burger, D., Alvisi, L.: Modeling the effect of technology trends on the soft error rate of combinational logic. In: International Conference on Dependable Systems and Networks, pp. 389–398 (2002)
Metadata
Title
An Efficient Model for Soft Error Vulnerability of Dynamic Circuits
Authors
Yan Sun
Yuesheng Cao
Jinwen Li
Tiejun Li
Copyright Year
2018
Publisher
Springer Singapore
DOI
https://doi.org/10.1007/978-981-10-7844-6_13