Architecture Exploration of FPGA Based Accelerators for BioInformatics Applications

Application-specific integrated circuits (ASICs) are specialized custom-designed circuits which are developed to carry out desired tasks efficiently in hardware. Often, microprocessors are preferred over ASICs, since they give flexibility to users. They allow the same hardware to be used for a variety of applications. Still for applications requiring very high speed computation and/or very low energy ASICs have been preferred over software solutions. Microprocessors are typically based on Von Neumann architecture, which allow execution of stored programs (Von Neumann, IEEE Ann. Hist. Comput. 15(4): 27–75, 1993). For implementing a specific application, the user writes software programs to specify the sequence of tasks that gets executed within the processor. Rapid advances in VLSI technology have enabled fabrication of billions of transistors on a single chip. Technology scaling has allowed number of transistors to double every 18 months in accordance to Moore’s law (Moore, Prod. IEEE 86(1):82–85, 1998). This technological advancement has led to design and development of faster and energy-efficient hardware. Availability of faster processors enabled software based solutions to replace hardware solutions over increasingly larger domain. In the past few years, frequency scaling of processors has saturated due to thermal limitations and the integrated circuit (IC) designers are focusing on gaining speedups by running more operations concurrently in hardware; either on multi-core processors or on specialized hardware.

In this chapter we discuss the related work, where we present some of the ideas and implementations reported by other researchers working in areas closely related to this field. First we describe the various accelerator architectures and then, discuss FPGA based accelerators. We describe the FPGA architecture as well as the EDA tool flow followed while exploring HEBs in FPGAs. We discuss “bioinformatics” domain and the two important applications belonging to this domain. We show how these applications have benefited by FPGA-based acceleration.

Many software implementation of applications have been accelerated using FPGAs. Compute intensive kernels from the application are implemented in hardware and executed in parallel to achieve speedup over softwares. FPGA consists of CLBs (consisting of LUTs and flip-flops) and interconnects which are programmable. HEBs implement performance critical components efficiently vis-a-vis their implementation using configurable logic and thus improve the performance. Adding of HEBs to FPGA fabrics may not always give performance benefits, as they occupy significant amount of chip area and sometimes may not be usable due to limitations of the memory bandwidth. A proper methodology to design HEBs and estimate the expected performance gain would be a necessary component of any design methodology. It is expected that more HEBs will be embedded into FPGAs and such a methodology will aid in building efficient reconfigurable fabrics. In this chapter, we describe a methodology to design accelerators using FPGAs with custom-designed HEBs.

In this chapter, we discuss FPGA-based acceleration of a commonly used protein docking application. The docking application is compute intensive and involves floating-point computations. We used the methodology discussed in Chap. 3 to accelerate the application. Accordingly, we explain the identification of kernel from the software implementation and their FPGA implementation to get performance benefits.

De novo Assembly is a method in which the genome is constructed using the reads without using reference sequence. It is the only way to construct new genomes. This method is also used when reference genome is available because the construction is unbiased. The genome assembly involves large amounts of data and string comparison and hence takes significant time to execute. In this chapter, we show achieved speedups over software implementations using FPGA-based accelerators.

In modern FPGAs, the digital circuitry common to many applications are being embedded as hard embedded blocks to utilize silicon area efficiently. Use of HEBs improves the overall performance of hardware implemented using FPGA, as the interconnect delays are also reduced. In this chapter, we discuss how HEBs are designed using the methodology described in Chap. 3. We study the impact of HEBs on the execution time of the two bioinformatics applications; Protein docking and Genome assembly. In Chaps. 4 and 5, we had studied the acceleration of these applications using currently available FPGAs. In this chapter, we discuss the identification and design of respective HEBs to get performance benefits. We also show how we can estimate application speedups using these future FPGA fabrics incorporating these HEBs.

In this chapter, we discuss the design space exploration carried out to accelerate de novo genome assembly using FPGAs. It is well known that as systems become more complex, one moves up the abstraction level for design space exploration through simulation. This is essential for managing complexity. Normally, higher abstraction levels imply faster and wider design space exploration but come at the price of lower accuracy. The focus of this chapter is on high-level design space exploration. The exploration was carried out at three levels. In this chapter, we propose modeling at three different levels: high-level algorithm model using ‘C’ followed by cycle-accurate model using System-C, and finally RTL component model using VHDL. We classify the parameters that can be studied using these three models.

New high-performance applications demand high compute power. These applications have always driven hardware designers to come up with new hardware architectures to execute them efficiently. On the other hand, today’s connected world with complex but standard interfaces require extensive software components to be integral part of any solution.