ASIF Hardware Generation

This chapter presents an automated method of generating hardware description of ASIF architectures. The ASIF hardware generator is integrated with the ASIF exploration environment. By doing so, all ASIF architectural parameters that are supported by the exploration environment are automatically supported by the VHDL generator. A bitstream generator is also integrated with the exploration environment. It generates programming bitstream for each netlist mapped on ASIF. These bitstreams can be individually programmed on the ASIF to execute different application circuits exclusively. The VHDL model of an ASIF is simulated using Synopsys. Bitstreams of different application circuits are programmed and tested on ASIF. The VHDL model is later passed to Cadence Encounter to generate layout of ASIFs for 130nm 6-metal layer CMOS process of ST Micro-Electronics.