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Published in:
2014 | OriginalPaper | Chapter
Chapter 17 Week 8 Class 2
Author : John Michael Williams
Published in: Digital VLSI Design with Verilog
Publisher: Springer International Publishing
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Abstract
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Lecture on verilog configurationsTopics: Libraries and
configs.Summary: We explain the relation of a library to a design and enumerate the major keywords for aconfig. There is no lab exercise or example available because of lack of vendor implementation. -
Lecture on timing arcs and specify delaysTopics: Timing arcs within modules,
specifyblocks, path and full delays.Summary: We build on the library concept to cover verilog delays within a module, especially a module for a library component. We elaborate on the use of lumped vs. distributed delays on a path. We presentspecifyblocks and their delay statements, includingspecparams, leaving timing checks for a later class. -
LabWe study details of specify-block delays, concentrating on resolution of conflicts among overlapping paths. We write out an SDF file after a synthesis.
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Lab PostmortemWe discuss simulation of conflicting delay specifications.