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2019 | OriginalPaper | Chapter

5. Charge Based Devices

Author : Hassan Raza

Published in: Nanoelectronics Fundamentals

Publisher: Springer International Publishing

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Abstract

In this chapter, we discuss ideal and nonideal conduction behavior of various two terminal and three terminal nanodevices based on semiconducting channels. The end of chapter problems encourage the enthusiastic reader to couple NEGF formalism from the previous chapter to the IV characteristics of the nanodevices discussed in this chapter. For the two terminal devices, the channel is connected to the source and the drain contacts, using which one may inject electrons or holes into the channel and extract electrons or holes out of the channel. Source and drain contacts are also referred to as cathode and anode, respectively, with reference to the electron injection and the extraction. For the three terminal devices, the third contact (called gate) is used to electrostatically control the channel to switch the device between ON and OFF states. The current through the gate contact is usually undesirable and hence termed as the gate leakage current.

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Footnotes
1
A nonvolatile memory keeps its memory state stored during power cycle, whereas a volatile memory looses information during power cycle.
 
2
Doping on the order of \(10^{18}-10^{20}\ \mathrm{cm}^{-3}\).
 
3
MOSFET is usually just written as MOS—a convention we also follow in this book unless otherwise necessary.
 
4
At equilibrium, one would have the same equilibrium chemical potential energy (\(\mu _o\)) throughout the device.
 
5
The superscript \(^{++}\) denotes degenerate doping.
 
6
\(V_\mathrm{DS}=V_\mathrm{D}-V_\mathrm{S}\). Usually, source contact in an nMOS is connected to ground and in a pMOS is connected to the supply voltage.
 
7
\(V_\mathrm{GS}=V_\mathrm{G}-V_\mathrm{S}\).
 
8
While we discuss electrostatic capacitance here, the discussion of quantum capacitance is beyond the scope of this book.
 
9
\(K_{ox}=3.9\) for silicon dioxide.
 
10
The region below the threshold voltage \((V_\mathrm{TN})\), i.e. \(V_\mathrm{G}<V_\mathrm{TN}\) for nMOS, is called subthreshold region.
 
Metadata
Title
Charge Based Devices
Author
Hassan Raza
Copyright Year
2019
DOI
https://doi.org/10.1007/978-3-030-32573-2_5

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