Skip to main content
Disciplines
Automotive Business IT + Informatics Construction + Real Estate Electrical Engineering + Electronics Energy + Sustainability Insurance + Risk Finance + Banking Management + Leadership Marketing + Sales Mechanical Engineering + Materials
Events
DE
EN
Books
Journals
Topic Page
Marketing
Start single access now
Access for companies
EXTENDED SEARCH
Log in
Top
Published in:
Introduction Read chapter Read first chapter

2018 | OriginalPaper | Chapter

4. Compilation Method of Reconfigurable Cryptographic Processors

Authors : Leibo Liu, Bo Wang, Shaojun Wei

Published in: Reconfigurable Cryptographic Processor

Publisher: Springer Singapore

Log in

Activate our intelligent search to find suitable subject content or patents.

search-config
loading …

Abstract

As an implementation of reconfigurable computing processors in specific fields, a reconfigurable cryptographic processor inherits the basic compilation framework of reconfigurable computing processors: The algorithm is described in high-level programming languages; the hardware and software partition is made through the static or dynamic analysis; then, the hardware part is transformed into the universal intermediate representation through the front-end compilation tools, which is then optimized through the middle-end compilation tools; finally, the mapping is implemented through back-end compilation tools including the synthesis tool, placement and routing tool, and the configuration information of the reconfigurable computing structure is generated. This chapter will be based on this framework and consider the particularity of the compilation method of reconfigurable cryptographic processors. As a cipher algorithm has many obvious code features such as the fixed-boundary loop, loop-carried data dependency, simple control flow, and quite different data granularity, the compilation method of the compiler of a reconfigurable cryptographic processor needs to be optimized based on these features. This chapter will start with general reconfigurable computing processors and introduce their universal compilation technologies and methods, including the main steps throughout compilation process. Then, this chapter will discuss the compilation methods of reconfigurable cryptographic processors, focusing on the steps which are very important for cipher application, such as code transformation and optimization, division and mapping of intermediate representations. Finally, this chapter will give examples about compilation and implementation of different cipher algorithms.

Dont have a licence yet? Then find out more about our products and how to get one now:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

inform now

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

inform now

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 340 Zeitschriften

aus folgenden Fachgebieten:

  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Versicherung + Risiko




Jetzt Wissensvorsprung sichern!

inform now
previous chapter Hardware Architecture of Reconfigurable Cryptographic Processors
next chapter Examples of Reconfigurable Cryptographic Processor Design
Literature
1.
Cardoso JMP, Diniz PC et al (2010) Compiling for reconfigurable computing: a survey. ACM Comput Surv 42(4):1–65CrossRef
2.
Li Z, Liu L (2017) Aggressive pipelining of irregular applications on reconfigurable hardware. In: International symposium on computer architecture CrossRef
3.
Mahlke SA, Lin DC, Chen WY et al (1993) Effective compiler support for predicated execution using the hyperblock. In: International symposium on microarchitecture, pp 45–54
4.
Girkar M, Polychronopoulos CD (1992) Automatic extraction of functional parallelism from ordinary programs. IEEE Trans Parallel Distrib Syst 3(2):166–178CrossRef
5.
Galloway D (1995) The transmogrifier C hardware description language and compiler for FPGAs. In: IEEE symposium on FPGAs for custom computing machines, p 136
6.
Agarwal L, Wazlowski M, Ghosh S (1994) An asynchronous approach to efficient execution of programs on adaptive architectures utilizing FPGAs. In: IEEE workshop on FPGAs for custom computing machines. IEEE, pp 101–110
7.
Weinhaudt M, Luk W (2002) Memory access optimisation for reconfigurable systems. IEE Proc Comput Digit Tech 148(3):105–112CrossRef
8.
Babb J, Rinard M, Moritz CA et al (1999) Parallelizing applications into silicon. In: IEEE symposium on field-programmable custom computing machines, pp 70–80
9.
Bondalapati K, Prasanna VK (1999) Dynamic precision management for loop computations on reconfigurable architectures. In: IEEE symposium on field-programmable custom computing machines, pp 249–258
10.
Gokhale M, Stone JM, Arnold JG et al (2000) Stream-oriented FPGA computing in the streams-C high level language. In: IEEE symposium on field-programmable custom computing machines, pp 49–56
11.
Yin C, Yin S, Liu L et al (2009) Compiler framework for reconfigurable computing system. In: International conference on communications, circuits and systems, pp 991–995
12.
Smith AL (2009) Explicit data graph compilation. The University of Texas at Austin doctoral dissertation, Austin
13.
Budiu M, Goldstein SC (1999) Fast compilation for pipelined reconfigurable fabrics. In: ACM/SIGDA international symposium on field programmable gate arrays, pp 195–205
14.
Mei B, Vernalde S, Verkest D et al (2003) ADRES: an architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix. In: International conference on field-programmable logic and applications, pp 61–70CrossRef
15.
Baumgarte V, Ehlers G, May F et al (2003) PACT XPP-a self-reconfigurable data processing architecture. J Supercomput 26(2):167–184CrossRef
16.
Benson J, Cofell R, Frericks C et al (2012) Design, integration and implementation of the DySER hardware accelerator into OpenSPARC. In: IEEE international symposium on high-performance computer architecture, pp 1–12
17.
Lattner C, Adve VS (2004) LLVM: a compilation framework for lifelong program analysis and transformation. In: International symposium on code generation and optimization, pp 75–86
18.
Ye ZA, Shenoy N, Baneijee P (2000) A C compiler for a processor with a reconfigurable functional unit. In: ACM/SIGDA international symposium on field programmable gate arrays, pp 95–100
19.
Callahan TJ, Hauser JR, Wawrzynek J (2000) The Garp architecture and C compiler. Computer 33(4):62–69CrossRef
20.
Gokhale M, Gomersall D (1997) High level compilation for fine grained FPGAs. In: IEEE symposium on field-programmable custom computing machines, pp 165–173
21.
Micheli GD (1994) Synthesis and optimization of digital circuits. McGraw-Hill, New York
22.
Budiu M, Sakr M, Walker K et al (2000) Bitvalue inference: detecting and exploiting narrow bitwidth computations. In: International Euro-Par conference on parallel processing, pp 969–979CrossRef
23.
Muchnick SS (1997) Advanced compiler design and implementation. Morgan Kaufmann, San Francisco
24.
Dongarra JJ, Hinds AR (2010) Unrolling loops in fortran. Softw Pract Exp 9(3):219–226CrossRef
25.
Hartenstein RW, Kress R (1995) A datapath synthesis system for the reconfigurable datapath architecture. In: Asia and South Pacific design automation conference, pp 479–484
26.
Lam MS (1988) Software pipelining: an effective scheduling technique for VLIW machines. ACM Sigplan Not 23(7):318–328CrossRef
27.
Hamzeh M, Shrivastava A, Vrudhula S (2012) EPIMap: using epimorphism to map applications on CGRAs. In: Design automation conference, pp 1280–1287
28.
Park H, Fan K, Mahlke S et al (2008) Edge-centric modulo scheduling for coarse-grained reconfigurable architectures. In: International conference on parallel architectures and compilation techniques, pp 166–176
29.
Park H, Fan K, Kudlur M et al (2006) Modulo graph embedding: mapping applications onto coarse-grained reconfigurable architectures. In: International conference on compilers, architecture and synthesis for embedded systems, pp 136–146
30.
Hamzeh M, Shrivastava A, Vrudhula S (2013) REGIMap: register-aware application mapping on coarse-grained reconfigurable architectures. In: Design automation conference, p 18
31.
Bastoul C (2004) Code generation in the polyhedral model is easier than you think. In: International conference on parallel architecture and compilation techniques, pp 7–16
32.
Bondhugula U, Hartono A, Ramanujam J et al (2008) A practical automatic polyhedral parallelizer and locality optimizer. ACM SIGPLAN Not 43(6):101–113CrossRef
33.
Cohen A, Sigler M, Girbal S et al (2005) Facilitating the search for compositions of program transformations. In: International conference on supercomputing, pp 151–160
34.
Hannig F, Dutta H, Teich J (2004) Mapping of regular nested loop programs to coarse-grained reconfigurable arrays-constraints and methodology. In: International parallel and distributed processing symposium, p 148
35.
Liu D, Yin S, Liu L et al (2013) Polyhedral model based mapping optimization of loop nests for CGRAs. In: Design automation conference, pp 1–8
36.
Liu D, Yin S, Peng Y et al (2015) Optimizing spatial mapping of nested loop for coarse-grained reconfigurable architectures. IEEE Trans Very Large Scale Integr Syst 23(11):2581–2594CrossRef
37.
Peterson JB, O’Connor RB, Athanas PM (1996) Scheduling and partitioning ANSI-C programs onto multi-FPGA CCM architectures. In: IEEE symposium on FPGAs for custom computing machines, pp 178–187
38.
Kum K, Kang J, Sung W (2000) Autoscaler for C: an optimizing floating-point to integer C program converter for fixed-point digital signal processors. IEEE Trans Circuits Syst II: Analog Digit Signal Process 47(9):840–848CrossRef
39.
Ong SW, Kerkiz N, Srijanto B et al (2001) Automatic mapping of multiple applications to multiple adaptive computing systems. In: IEEE symposium on field-programmable custom computing machines, pp 10–20
Metadata
Title
Compilation Method of Reconfigurable Cryptographic Processors
Authors
Leibo Liu
Bo Wang
Shaojun Wei
Copyright Year
2018
Publisher
Springer Singapore
Book
Reconfigurable Cryptographic Processor

Print ISBN: 978-981-10-8898-8

Electronic ISBN: 978-981-10-8899-5

Copyright Year: 2018

DOI
https://doi.org/10.1007/978-981-10-8899-5_4