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Published in:
2007 | OriginalPaper | Chapter
Compiler-Directed Dynamic CPU Frequency and Voltage Scaling
Authors : Chung-Hsing Hsu, Ulrich Kremer
Published in: Designing Embedded Processors
Publisher: Springer Netherlands
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This paper presents the design, implementation, and evaluation of a compiler algorithm that effectively optimizes programs for energy usage using dynamic voltage and frequency scaling (DVFS). The algorithm identifies program regions where the CPU can be slowed down with negligible performance loss, and has been implemented as a source-to-source level compiler transformation using the SUIF2 compiler infrastructure. Physical measurements on a notebook computer show that total
system
energy savings of up to 28% can be achieved with performance degradation of less than 5% for the SPEC CPU95 benchmarks. On average, the system energy and energy-delay product are reduced by 11% and 9%, respectively, with a performance slowdown of 2%.