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Published in:
2023 | OriginalPaper | Chapter
Connecting IPs
Author : Bernard Goossens
Published in: Guide to Computer Processor Architecture
Publisher: Springer International Publishing
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This chapter presents the AXI interconnection system. You will build two multi-IP components. The different IPs are connected via the AXI interconnect IP provided by the Vivado component library. The first design connects a rv32i_npp_ip processor (presented in Chap. 6 ) to two block memories, one for code and the other for data. This design is intended to show how the AXI interconnection system works. The second design connects two IPs sharing two data memory banks. It is intended to show how multiple memory blocks are shared by multiple IPs, using the AXI interconnection to exchange data.