Design and Simulation of High-Performance 2D Convolution Architecture

Two-dimensional 2-D convolution is always computationally intensive and memory-intensive process. There are many architectures to handle the computational load of 2D convolution constrained by its throughput, area requirement and memory bandwidth. All the architecture tried to optimize one of the three parameters keeping the others unbounded. This paper presents a new design of 2D convolution with new features to improve throughput, efficient data reuse to keep the area minimum. The design uses the principle of Double Data Rate register to use two clocks of the same period but opposite phase. Unlike legacy architecture using multiple window convolutions for throughput, the proposed design uses only 2 windows which triggers on the positive edge of two clocks, one after the other giving the throughput of 2 pixel/clock while keeping the area and memory bandwidth minimum.