7. Design Case

A power-efficient 14-bit 150 MSps ADC is presented in this chapter. Range scaling enables a maximal 2-\(\text {V}_{p-p}\) input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multiplying digital-to-analog converter (MDAC) and the second one reduces the total opamp power further. The dedicated sample-and-hold amplifier (SHA) is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the performance. The prototype ADC is fabricated in a 130 nm CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 mW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.