Design of Energy Efficient Multiplier with Approximate Computing on Scalable Compressor for Error-Resilient Image Contrast Enhancement

A number of arithmetic operations and applications use digital logic circuits as their primary building blocks, to operate with high reliability and precision. The multiplier is the core part of most arithmetic designs. The trend of imprecise multiplier has gained visibility in recent years, especially for image processing applications. Most of the multiplier designs use a compressor in the dot product reduction. In recent years, researchers have focused on designing imprecise, or approximate compressor to reduce design complexity while maintaining a low error rate. For higher bit multiplication, the design of a higher-order compressor is required. Using Karnaugh map (K-map) and truth table for approximation is a challenging task for the higher-order compressor. To address this issue, a scalable compressor with reasonable approximation using counter-based comparison methods is designed in this paper. The simulation results used with scalable compressors are compared with the existing 8 × 8 and 16 × 16 multipliers. These approximate circuits show significant improvement in the efficiency of multimedia signal processing, leading to better efficiency in terms of 30% area, 25% power, 20% delay, mean error distance (MED), error distance (ED), and normalized error distance (NED). The proposed method is applied in image multiplications for image contrast enhancement application. The peak signal-to-noise ratio (PSNR) is then determined and compared to other existing work.