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2016 | Book

Introduction Read chapter Read first chapter

Digital Logic Design Using Verilog

Coding and RTL Synthesis

Author: Vaibbhav Taraate

Publisher: Springer India

Part of: Springer Professional "Wirtschaft+Technik" , Springer Professional "Technik" , Springer Professional "Wirtschaft"

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About this book

This book is designed to serve as a hands-on professional reference with additional utility as a textbook for upper undergraduate and some graduate courses in digital logic design. This book is organized in such a way that that it can describe a number of RTL design scenarios, from simple to complex. The book constructs the logic design story from the fundamentals of logic design to advanced RTL design concepts. Keeping in view the importance of miniaturization today, the book gives practical information on the issues with ASIC RTL design and how to overcome these concerns. It clearly explains how to write an efficient RTL code and how to improve design performance. The book also describes advanced RTL design concepts such as low-power design, multiple clock-domain design, and SOC-based design. The practical orientation of the book makes it ideal for training programs for practicing design engineers and for short-term vocational programs. The contents of the book will also make it a useful read for students and hobbyists.

Table of Contents

Frontmatter
Chapter 1. Introduction
Abstract
This chapter discusses about the overview of the design abstraction levels and the evolution of logic design in the perspective of the system design. This chapter is mainly focused on the familiarity with Verilog HDL, different modeling styles, and Verilog operators. The chapter is organized in such a way that it covers basic to the practical scenarios in detail. All the Verilog operators with meaningful examples are described in this chapter for easy understanding.
Vaibbhav Taraate
Chapter 2. Combinational Logic Design (Part I)
Abstract
This chapter describes the use of Verilog HDL to code the combinational logic design and covers the small gate count designs. The chapter is organized in such a way that it can give the practical synthesizable Verilog HDL understanding with key practical scenarios and applications. The synthesizable Verilog HDL is described for the required functionality and the synthesized logic is explained for practical understanding. This chapter is useful to build the practical expertise to code the combinational designs using synthesizable Verilog constructs.
Vaibbhav Taraate
Chapter 3. Combinational Logic Design (Part II)
Abstract
This chapter describes the complex combinational logic designs and covers the detail and practical oriented scenarios while describing the multiplexers, decoders, encoders, and priority encoders. The use of constructs like ‘‘if-else,’’ ‘‘case,’’ and continuous assignment ‘‘assign’’ are described in detail with the meaningful practical examples. The main focus of this chapter is to describe the design functionality with the synthesizable logic. Even this chapter focuses on the key practical issues need to be tackled while describing the Verilog HDL.
Vaibbhav Taraate
Chapter 4. Combinational Design Guidelines
Abstract
This chapter describes about the design guidelines for the combinational logic designs. In the practical ASIC designs, these guidelines are used to improve the readability, performance of the design. The key practical guidelines discussed are use of ‘if-else’ and ‘case’ constructs and the practical scenarios, how to infer the parallel and priority logic. The detailed practical use of resource sharing and use of blocking assignments to describe the combinational logic design is explained in detail. The chapter key highlight is the description of the stratified event queuing and logical partitioning. This chapter also describes the scenarios of missing else, default in the sequential statements and combinational looping in the design. All the guidelines in this chapter are covered with the meaningful practical examples and the synthesized logic is explained for better understanding.
Vaibbhav Taraate
Chapter 5. Sequential Logic Design
Abstract
This chapter describes the detail practical understanding about the sequential logic designs. RTL coding using Verilog is described in detail with the practical scenarios and concepts. The Verilog RTL for the flip-flops, latches, various counters, shift registers, and memories is covered with the synthesized results and explanations. The practical do’s and don’ts are explained with the meaningful diagrams and timing sequences. This chapter will be useful for the ASIC designers while coding for the sequential logic. This chapter also covers the necessity of registered input and register outputs.
Vaibbhav Taraate
Chapter 6. Sequential Design Guidelines
Abstract
This chapter describes about the key sequential design guidelines used in the ASIC design. These guidelines are essential for any ASIC design and used to improve the readability, performance, and need to be followed by an ASIC design engineer. The key guideline includes the use of nonblocking assignments in sequential designs, the use of synchronous resets and clock gating. The guidelines to use the pipelined stages in the design are described in detail and useful for improving the design performance. This chapter also covers the basic information about describing the Verilog RTL with multiple clocks, multiphase clocks and the issues with asynchronous resets.
Vaibbhav Taraate
Chapter 7. Complex Designs Using Verilog RTL
Abstract
The complex ASIC designs can be described by using the Verilog RTL. In the practical scenario the objective is to describe the design functionality by using efficient Verilog RTL by using key and important combinational and sequential design guidelines. This chapter focuses on the discussion to describe the complex designs like ALU, parity generators, checkers, and barrel shifters. This chapter also discusses about the synthesized logic with the data path and control paths. The complex examples are explained in this chapter with practical aspects and with the diagrams and functional tables. This chapter is useful for ASIC and FPGA designers to understand the issues like combinational designs, critical paths, register inputs, and outputs.
Vaibbhav Taraate
Chapter 8. Finite State Machines
Abstract
Finite state machine (FSM) is source synchronous sequential designs where every register is triggered on the active edge of clock. The two types of state machines are Moore and Mealy. This chapter discusses about the efficient and synthesizable FSM coding using Verilog RTL. The key differences between the Moore and Mealy machines as well as different FSM encoding styles are discussed in detail. This chapter illustrates the Verilog RTL examples with the multiple ‘always’ blocks to represent the efficient state machines. This chapter also focuses on the do’s and don’ts while coding FSM. The FSM design performance improvement with the key guidelines is also described in this chapter.
Vaibbhav Taraate
Chapter 9. Simulation Concepts and PLD-Based Designs
Abstract
Programmable logic devices (PLDs) are used extensively in the research areas and even in the industrial applications to realize the complex designs due to programmability features. PLDs are used to prototype the ASIC SOCs due to the availability of the configurable logic blocks, multipliers, and DSP blocks. This chapter discusses about the PLD evolution, architecture of FPGA, and why to use FPGA, FPGA design guidelines and the logic realization using FPGAs. Even this chapter discusses about the simulation constructs and the different delays with the basic testbench.
Vaibbhav Taraate
Chapter 10. ASIC RTL Synthesis
Abstract
Application Specific Integrated Circuit (ASIC) is designed for the specific purpose. The ASIC design flow can be used to design the full-custom or semi-custom designs. This chapter discusses about the different types of ASIC, ASIC design flow key steps, and the RTL synthesis. The design optimization techniques and the Synopsys Design Compiler commands are covered in this chapter with relevant examples. This chapter also discusses about key Verilog RTL modifications to reduce the compiler time during synthesis.
Vaibbhav Taraate
Chapter 11. Static Timing Analysis
Abstract
Static timing analysis (STA) is used for the timing checks for any ASIC designs. The objective of this chapter is to discuss in detail STA concepts used by the timing analyzer. This chapter discusses about the register timing parameters and their use in the frequency calculations. The positive clock skew and negative clock skew are also discussed in detail with the practical scenario. This chapter also focuses on the different timing paths and SDC commands and their use while writing the script. The solutions and techniques to fix the setup and hold violations are also discussed for the better understanding of the engineers. Even the timing exceptions like false and multicycle paths are covered with the practical scenario.
Vaibbhav Taraate
Chapter 12. Constraining ASIC Design
Abstract
This chapter discusses about the constraining design using Synopsys DC compiler. Every ASIC design needs to meet the constraints. The constraints are classified as optimization, design rule, and environmental constraints. This chapter covers the area minimization techniques, design optimization techniques using the meaningful practical design scenarios. Even this chapter describes about the key important commands used to boost the design performance. This chapter even discusses about the commands used for the FSM extractions. The sample scripts are given in the chapter and can be used for the design optimization and the report generations.
Vaibbhav Taraate
Chapter 13. Multiple Clock Domain Design
Abstract
In the practical ASIC and SOC designs the multiple clocks are used and the designs are called as multiple clock domain designs. These kinds of designs need to be described using the efficient design architectures and Verilog RTL. This chapter focuses in the key design techniques which are used to describe the multiple clock domain designs while passing data from one of the clock domain to other. The chapter key highlights are the detail description for the synchronizers, data path, and control path synchronization logic using the efficient Verilog RTL. This chapter also discusses on the key design challenges in the multiple clock domain designs and even this chapter focuses on the design guidelines to describe the efficient clock domain designs.
Vaibbhav Taraate
Chapter 14. Low Power Design
Abstract
In the modern lower process node ASIC design the power is considered as the major factor. The low power design chips are required in many applications like mobile, computing, processing, and video and audio controller designs. Most of the SOC designs need the low power design support. This chapter discusses abut the low power design techniques at the RTL level and the use of the consistent format UPF at the logical design. This chapter is useful for the RTL design engineers to understand the UPF terminology and the key commands for inclusion of the level shifter, retention, and isolation cells. Even this chapter describes about the multiple power domain creation with the UPF commands.
Vaibbhav Taraate
Chapter 15. System on Chip (SOC) Design
Abstract
SOCs are complex density ASICs and need to be validated using the FPGAs. In the present scenario there is more demand for the FPGA prototyping to realize the ASICs. Single or multiple FPGA can be used to prototype the desired SOC functionality. This chapter focuses on the discussion on the SOC components, challenges, and the SOC design flow. Even the individual key SOC block coding is discussed in this chapter.
Vaibbhav Taraate
Backmatter
Metadata
Title
Digital Logic Design Using Verilog
Author
Vaibbhav Taraate
Copyright Year
2016
Publisher
Springer India
Electronic ISBN
978-81-322-2791-5
Print ISBN
978-81-322-2789-2
DOI
https://doi.org/10.1007/978-81-322-2791-5