Efficient Sensor Interfaces, Advanced Amplifiers and Low Power RF Systems

This paper describes a dynamic element matching (DEM) algorithm, the so-called Smart-DEM (SDEM) algorithm, suitable for multi-bit incremental converters. The effectiveness of the algorithm is studied and compared with conventional DEM methods at the behavioural level with the help of two case studies. The paper, moreover, presents the design and the experimental verification of a second-order 3-bit incremental converter which employs the SDEM algorithm to compensate for the mismatch among unity elements of its multi-level digital-to-analog converter (DAC). The circuit, fabricated in a mixed 0.18–0.5 \(\upmu\) m CMOS technology, achieves a resolution of 16.7 bit over a 5-kHz bandwidth by using 256 clocks periods per sample.

Integrated sensor interfaces require energy-efficient high-resolution data converters. In many applications, the best choice is to use incremental analog-to-digital converters (IADCs) incorporating variants of extended counting. In this chapter, we discuss the design of a micropower IADC. By using a feed-forward architecture, the IADC accumulates the residue voltage, so various hybrid variants of extended counting can be implemented. Several such schemes are reviewed and discussed, as well as the trade-off between higher order modulators, higher oversampling ratio and energy efficiency. A two-step IADC is proposed, which extends the performance of an Nth-order IADC close to that of a (2N − 1)th-order IADC. A design example uses the circuitry of a second-order IADC to achieve a performance nearly equal to that of a third-order IADC. The implemented IADC achieves a measured dynamic range of 99.8 dB, and a SNDR of 91 dB for a maximum input 2.2 V_PP and a bandwidth of 250 Hz. Fabricated in 65 nm CMOS and operated from a 1.2 V power supply, the IADC’s core area is 0.2 mm², and it consumes only 10.7 μW. The measured FoMs are 0.76 pJ/conv.step and 173.5 dB, both among the best reported results for IADCs.

Multiple energy-efficient CDCs are proposed for millimeter sensor nodes. Compared to the state-of-the-art, these CDCs achieves excellent energy efficiency, high SNR, and wide input range with a variety of techniques. These include correlated double sampling in front of a SAR ADC, incremental delta-sigma conversion with a zoom-in SAR converter, energy-efficient dual-slope conversion, and fully-digital iterative delay-chain discharge conversion.

This paper describes the design of a low-power energy-efficient temperature-to-digital converter (TDC) intended for the temperature compensation of a 32 kHz MEMS-based oscillator (TCXO). The compensation scheme enables a frequency stability of ±3 ppm over temperatures ranging from −40 to 85 °C. The TDC consists of an NPN-based temperature sensing element and a 15-bit second order ΔΣ modulator. A novel dynamic element matching (DEM) scheme ensures that DEM tones do not inter-modulate with the modulator’s bit-stream, thus improving the TDC’s accuracy without impacting its resolution. The TDC occupies 0.085 mm² in a 180 nm CMOS process, draws less than 4.5 μA from a 1.5 to 3.3 V supply, and achieves a resolution of 25 mK in a conversion time of 6 ms. This corresponds to a figure of merit of 24 pJ°C².

The design of energy efficient instrumentation has long been fueled by the mobile applications where low-power sensors and sensor interfaces have been used for continuous measurement of inertial measurements and environmental parameters. On the other hand, during the last decade, together with the increasing interest on continuous measurements of physiological and neural signals, new generations of energy efficient instrumentation amplifiers have emerged. This paper presents the state of the art of instrumentation architectures in the field of biomedical instrumentation and discusses their use in wearable and implantable biomedical signal acquisition systems.

Smart and miniaturized implantable microsystems with diagnostic and therapeutic capabilities are becoming increasingly important for patients suffering from neurological disorders such as epilepsy. Recent developments in microfabrication technology have provided new insights into seizure generation at an unprecedented spatial scale. Based on these findings, designing powerful acquisition systems capable of probing the wide-range spatiotemporal activities within the brain holds a great promise to improve the quality of life of epileptic patients. As a major technological barrier, the high overall data rate of digitized neural signals recorded by dense electrode arrays can drastically increase the power consumption of the wireless transmission module. Consequently, extensive system-level design improvement is needed to meet the requirements of the implantable device, while preserving the high-resolution monitoring capability. In this context, low-power circuit and system design techniques for data compression and seizure detection in multichannel cortical implants are presented. The first fully-integrated circuit that addresses the multichannel compressed-domain feature extraction is proposed, consuming sub-\(\upmu\) W of power within an effective area of \(250\,\upmu \mathrm{m} \times 250\,\upmu \mathrm{m}\) per channel.

This Operational amplifiers have been the backbone of most amplifiers and filters in communication applications and ADCs. They are in competition with Gm blocks for higher frequencies despite their higher linearity. Both of them are now gradually being replaced by CMOS inverters. This text focuses on the merits and advantages of all three of them.

Amplifiers that need to drive heavy loads (low resistances and/or large capacitances) with good efficiency generally use a push-pull output stage. This intrinsically creates large open-loop distortion components that need to be compressed through feedback to insure high closed-loop linearity. Minimizing close loop residual distortion involves three steps that will be discussed in this chapter. Eliminate all open-loop source of distortion not intrinsic to the proper operation of the push pull structure. Second, choose the amplifier topology that gives the maximum close loop compression of the open-loop distortion components for a given bandwidth. Third, maximize the open-loop gain in the signal band and/or the unity gain bandwidth of the amplifier for a given topology while insuring stability in the presence of variable loads.

This paper discusses the design strategy of an acquisition chain for microphone input signal. First, target specifications are given. The overall strategy for the acquisition of the signal, pre-amplification and A/D conversion is then discussed, together with the main constraints, and a new architecture for the loop is proposed. The most critical analog blocks, such as first amplification stage, loop filter and biasing circuitry, are then investigated in more details, followed by measurement results.

This paper address two main aspects of the design of High Voltage Operational Amplifiers, both oriented to obtain high linearity. The first one is related to extend the bandwidth working on the transconductance as functions of the strongly nonlinear parasitic capacitance. The second describes a technique to draw the integrated feedback network based on a resistive voltage divider with particular focus to low power dissipation and high linearity.

This paper focuses on the design of amplifiers that achieve micro-volt offset by employing dynamic offset reduction techniques, which include chopping, auto-zeroing and chopper stabilization. The working principles and non-idealities of these techniques will be described. The up-modulated offset associated with chopping causes ripple, which can be a significant source of error if not filtered effectively. Thus, various ripple reduction techniques are introduced to suppress this ripple to the micro-volt level. Also discussed is the ping-pong architecture, which enables the realization of auto-zeroed amplifiers with continuous-time behavior. Examples of chopped amplifiers, auto-zeroed amplifiers and chopper stabilized amplifiers are presented, as well as designs in which multiple techniques are combined.

Integrated circuits and devices have been a cornerstone in the recent discovery of the Higgs boson by the ATLAS and CMS experiments at the Large Hadron Collider (LHC) at the European Laboratory for High Energy Physics (CERN) in Geneva. Particles are accelerated and brought into collision at well-defined interaction points. Detectors, giant cameras of about 40 m long by 20 m in diameter, constructed around these interaction points take pictures of the collision products as they fly away from the interaction point. They contain millions of channels often generating a small (∼1 fC) electric charge upon particle traversals. Integrated circuits provide the readout in a very aggressive radiation environment and accept collision rates of about 40 MHz with on-line selection of potentially interesting events before data storage. Power consumption directly impacts the measurement quality as it governs the amount of material present in the detector, and often the fraction of the power consumed by the front end amplifiers is significant if not predominant. We present basic architectures and a selection of front end amplifiers we hope as a representative overview for various types of particle detectors operated at LHC.

The PLL based frequency synthesizer has been the main impediment to achieve a low energy dissipation in the radios employed in Wireless Sensor Networks (WSN); in spite of duty cycling. This is due to the crystal oscillator reference in the frequency synthesizer which dissipates significant energy during its long wakeup phase. To address this issue and thereby obtain the full advantage proffered by duty cycling, an overview of FBAR based synthesizers which can wake up in just 5 μs is presented. In addition, these synthesizers can also support high data rates as compared to the PLL based radios, thereby offering the possibility to increase the rate of duty cycling and thus further lowering the average energy dissipation.

This paper discusses the key features and technical considerations in the design of ultra-low power wireless system-on-chips (SoC) for wireless body area networks (WBAN). The requirements of these sensor nodes, primarily for wearable professional medical monitoring applications, together with the available protocols governing the over-the-air communications are introduced. Furthermore, analysis of the major facets of the SoC system architecture and circuit building blocks will be covered, and presented in conjunction of a practical case-study of a complete multi-standard WBAN SoC fabricated in 65 nm CMOS technology operating in the 2.36–2.5 GHz frequency band.

N-path filters can offer high-linearity high-Q channel selection filtering at a flexibly programmable RF center frequency, which is highly wanted for Software Defined Radio. Relying on capacitors and MOSFET switches, driven by digital non-overlapping clocks, N-path filters fit well to CMOS and benefit from Moore’s law. The basis of this filtering is the linear periodically time variant (LPTV) behaviour of a switch-R-C series circuit, which realizes frequency translated filtering, where a baseband filter characteristic is shifted around the switching frequency. This paper reviews the basic concept of N-path filters and recent developments, with special attention to possibilities to reduce power consumption by increasing the impedance level. The basic operation of the switch-R-C kernel that is at the core of N-path filtering is reviewed in terms of transfer function and noise performance.

Some important aspects of CMOS RF PA design are discussed. First the reader is confronted with the ever prominent efficiency-linearity trade-off in the design of conventional amplifier classes, such as A and B, as well as the challenge to achieve high output power in low-voltage CMOS. To cope with this challenge, several power combining structures are introduced. Next, some RF PA architectures are presented to improve the efficiency at power back-off. Finally, some recently introduced architectures are discussed that use the advanced signal processing capabilities of CMOS to deal with this efficiency-linearity trade-off in RF PA design.

This paper presents an ultra-low power 2.4 GHz FSK/PSK RX for wireless personal/body area networks. An energy-efficient single-channel phase-domain receivers based on a sliding-IF phase-to-digital conversion (SIF-PDC) loop is presented. It equivalently transforms the signal processing from analog I/Q domain to the digital phase domain, which save almost 40 % power consumption. A phase rotator is employed in the phase-tracking loop to decouple the carrier generation and frequency demodulation, which guarantees the frequency stability and enables wideband operation. The analog multiplier and the single-bit quantization implementation improves the interference rejection. Fabricated in a 90 nm CMOS technology, the presented RX consumes 2.4 mW at 2 Mbps data rate, i.e., 1.2 nJ/b efficiency, and achieves a sensitivity of −92 dBm.

In this work, we will present a wake-up controller system complete with UHF and LF transceivers. Typical targeted applications are automotive remote/passive keyless entry key-fob and central unit solutions. Details for the implementation of the UHF transceiver front-end and signal processing are given that demonstrate the desired versatility in frequency, data rate and output power configurations.