4. Electromagnetic Noises

VLSI chips in a practical system always experience interactions with surrounding electromagnetic (EM) environment. EM noise emitted from circuits can interfere with other circuits on the same chip or in another chip. Circuits and systems performance may be unpredictably and dynamically degraded by EM noise through its impacts on power and signal integrity.This chapter discusses the state-of-the-art knowledge and countermeasures associated with such unseen noise problems, covering noise emission, noise immunity, noise mitigation, tolerance, and integrity, all for the noise awareness in the design of dependable VLSI systems.An overview of EM compatibility (EMC) in CMOS digital integrated circuits (ICs) is given in Sect. 4.1, along with simulation and measurements of EM noise in a semiconductor IC chip. EM noise emission is explained as the interaction of dynamic power currents in ICs and parasitic impedance in a chip-package-board combined power delivery network (PDN).Electromagnetic susceptibility (EMS) of IC chips against incoming radio frequency high-power disturbance is discussed in Sect. 4.2. Static random access memory (SRAM) cores are chosen for demonstrating EMS evaluation based on direct power injection (IEC 62132-4). On-chip waveform monitoring provides useful means to analyze the mechanisms in which incoming RF power causes SRAM bit failures.On-chip power supply filtering adaptively suppresses EM noise due to PDN resonance, as a proactive measure for reducing electromagnetic interference (EMI) of IC chips, discussed in Sect. 4.3.The 4b/10b is a dependable line code with error correction ability. Responsive Link, which is a real-time communication link, can control the trade-off among the error correction strength, throughput, and latency, based on the communication environment such as inside a high-power robot operated by extremely high voltage (80 V) and huge current (200 A), by selecting a line code including the 4b/10b, a bit-level error correction code, and a block-level error correction code, as demonstrated in Sect. 4.4.