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Published in:
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2010 | OriginalPaper | Chapter

2. Extreme Statistics in Memories

Author : Amith Singhee

Published in: Extreme Statistics in Nanoscale Memory Design

Publisher: Springer US

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Abstract

Memory design specifications typically include yield requirements, apart from performance and power requirements. These yield requirements are usually specified for the entire memory array at some supply voltage and temperature conditions. For example, the designer may be comfortable with an array failure probability of one in a thousand at 100°C and 1 V supply; i.e., F f,array ≤ 10−3. However, how does this translate to a yield requirement for the memory cell? What is the maximum cell failure probability, F f,cell, allowed so as to satisfy this array failure probability requirement? We will answer these questions and in the process understand the relevance of extreme statistics in memory design.

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previous chapter Introduction
next chapter Statistical Nano CMOS Variability and Its Impact on SRAM
Literature
1.
Joshi B, Anand RK, Berg C, Cruz-Rios J, Krishnamurthi A, Nettleton N, Nguyen S, Reaves J, Reed J, Rogers A, Rusu S, Tucker C, Wang C, Wong M, Yee D, Chang J-H (1992) A BiCMOS 50 MHz cache controller for a superscalar microprocessor. In: International Solid-State Circuits Conference, 1992
Metadata
Title
Extreme Statistics in Memories
Author
Amith Singhee
Copyright Year
2010
Publisher
Springer US
Book
Extreme Statistics in Nanoscale Memory Design

Print ISBN: 978-1-4419-6605-6

Electronic ISBN: 978-1-4419-6606-3

Copyright Year: 2010

DOI
https://doi.org/10.1007/978-1-4419-6606-3_2