Fault tolerance designs of interconnection networks

Multiprocessor interconnection networks are mainly required to link a significant number of stable processor memory sets, every one of which is known as a processing vertex. Due to the cost-effectiveness, the design and utilization of multiprocessor interconnection networks have drawn attention lately. An interconnection network is extensively used in a parallel multiprocessor system to connect the processors and memory modules. In multiprocessor networks, vertices represent processors, and each processor of which is subject to complete failure. Fault tolerance is a process that ensures the working of a system to its total capacity, even if one or more of its components fail. In fault-tolerant design, backup components are used in interconnection networks to automatically take the place of the failed component, guaranteeing that the system’s working continues. This paper proposed the fault-tolerant design in the form of \(P_j^k\) and \(C_j^k\) graphs, where n processing components are linked, and i of these n components creating a chain of maximum size, are used to perform the task, they can tolerate the failure of components, maintaining steady operation. In particular, we present the fault-tolerant designs of pyramid, OTIS, biswapped, and mesh-derived networks.