FIR and IIR Filter Design Using Modified Dadda Multiplier

Filters are an integral part of Digital Signal Processors (DSPs), which are necessary for signal processing in digital devices. DSPs are required to process sound signals to provide meaningful data and they are also required to process images captured by digital cameras. Multipliers and adders together form most parts of a filter. Existing filter architectures utilize various multipliers like Array multiplier, Wallace multiplier, Vedic multiplier, etc. These multipliers have a high delay resulting in performance degradation of the filters. Thus, an improvement in the architecture of the multiplier results in the betterment of the overall performance of the filters. The multipliers in turn can be improved by making changes in the algorithm used for the reduction of partial products and also by making changes to the architecture of the adder. For this purpose, a modified Dadda multiplier in which the final addition is done using the Kogge-Stone adder is being proposed in this work. The designed multiplier is an 8-bit multiplier that takes in 9-bit signed magnitude values as input and gives out 23-bit outputs which are then added together for the output to be produced. The FIR and IIR systems have been designed using VHDL and implemented in Vivado 2017.4 to obtain results.