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Published in: Wireless Personal Communications 4/2021

16-02-2021

Floor Planning of 3D IC Design Using Hybrid Multi-verse Optimizer

Authors: Sivakumar Pothiraj, Jeya Prakash Kadambarajan, Pandiaraj Kadarkarai

Published in: Wireless Personal Communications | Issue 4/2021

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Abstract

Several research works have been undergone in the 3D IC floor planning concepts due to its higher demand and technological improvement. Floor planning is a complex step when there is a more number of a component on each layer of IC. Even though several researches have been done in this area, the optimization process is still not satisfied with the use of traditional mechanisms. Consequently, there is a need for effective optimization procedure in IC design. Hence, in this proposed work, hybrid multi verse optimizer floor planning is utilized where the node coordinates and dimensions are adjusted to attain the optimized floor planning with minimal wire length and area using best universes.

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Literature
1.
go back to reference Davis, W. R., Wilson, J., Mick, S., Xu, J., Hua, H., Mineo, C., et al. (2005). Demystifying 3D ICs: The pros and cons of going vertical. IEEE Design & Test of Computers, 22, 498–510.CrossRef Davis, W. R., Wilson, J., Mick, S., Xu, J., Hua, H., Mineo, C., et al. (2005). Demystifying 3D ICs: The pros and cons of going vertical. IEEE Design & Test of Computers, 22, 498–510.CrossRef
2.
go back to reference Chiang, T.-Y., Souri, S. J., Chui, C. O., & Saraswat, K. C. (2001). Thermal analysis of heterogeneous 3D ICs with various integration scenarios. In International electron devices meeting. Technical digest (Cat. No. 01CH37224) (pp. 31.2.1–31.2.4). Chiang, T.-Y., Souri, S. J., Chui, C. O., & Saraswat, K. C. (2001). Thermal analysis of heterogeneous 3D ICs with various integration scenarios. In International electron devices meeting. Technical digest (Cat. No. 01CH37224) (pp. 31.2.1–31.2.4).
3.
go back to reference Cong, J., Wei, J., & Zhang, Y. (2004). A thermal-driven floorplanning algorithm for 3D ICs. In Proceedings of the 2004 IEEE/ACM international conference on computer-aided design (pp. 306–313). Cong, J., Wei, J., & Zhang, Y. (2004). A thermal-driven floorplanning algorithm for 3D ICs. In Proceedings of the 2004 IEEE/ACM international conference on computer-aided design (pp. 306–313).
4.
go back to reference Zhou, P., Ma, Y., Li, Z., Dick, R. P., Shang, L., Zhou, H., et al. (2007). 3D-STAF: Scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits. in Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design (pp. 590–597). Zhou, P., Ma, Y., Li, Z., Dick, R. P., Shang, L., Zhou, H., et al. (2007). 3D-STAF: Scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits. in Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design (pp. 590–597).
5.
go back to reference Sivaranjani, P., & Senthil Kumar, A. (2017). Hybrid particle swarm optimization-firefly algorithm (HPSOFF) for combinatorial optimization of non-slicing VLSI floorplanning. Journal of Intelligent & Fuzzy Systems, 32, 661–669.CrossRef Sivaranjani, P., & Senthil Kumar, A. (2017). Hybrid particle swarm optimization-firefly algorithm (HPSOFF) for combinatorial optimization of non-slicing VLSI floorplanning. Journal of Intelligent & Fuzzy Systems, 32, 661–669.CrossRef
6.
go back to reference Hung, W.-L., Xie, Y., Vijaykrishnan, N., Addo-Quaye, C., Theocharides, T., & Irwin, M. J. (2005). Thermal-aware floorplanning using genetic algorithms. In Sixth international symposium on quality electronic design (isqed'05) (pp. 634–639). Hung, W.-L., Xie, Y., Vijaykrishnan, N., Addo-Quaye, C., Theocharides, T., & Irwin, M. J. (2005). Thermal-aware floorplanning using genetic algorithms. In Sixth international symposium on quality electronic design (isqed'05) (pp. 634–639).
7.
go back to reference Nakatake, S., Fujiyoshi, K., Murata, H., & Kajitani, Y. (1997). Module placement on BSG-structure and IC layout applications. In Proceedings of the 1996 IEEE/ACM international conference on computer-aided design (pp. 484–491). Nakatake, S., Fujiyoshi, K., Murata, H., & Kajitani, Y. (1997). Module placement on BSG-structure and IC layout applications. In Proceedings of the 1996 IEEE/ACM international conference on computer-aided design (pp. 484–491).
8.
go back to reference Dong, S., Hong, X., Wu, Y., Lin, Y., & Gu, J. (2001). VLSI block placement using less flexibility first principles. In Proceedings of the 2001 Asia and South Pacific design automation conference (pp. 601–604). Dong, S., Hong, X., Wu, Y., Lin, Y., & Gu, J. (2001). VLSI block placement using less flexibility first principles. In Proceedings of the 2001 Asia and South Pacific design automation conference (pp. 601–604).
9.
go back to reference Guo, P.-N., Cheng, C.-K., & Yoshimura, T. (1999). An O-tree representation of non-slicing floorplan and its applications. In Proceedings 1999 design automation conference (Cat. No. 99CH36361) (pp. 268–273). Guo, P.-N., Cheng, C.-K., & Yoshimura, T. (1999). An O-tree representation of non-slicing floorplan and its applications. In Proceedings 1999 design automation conference (Cat. No. 99CH36361) (pp. 268–273).
10.
go back to reference Sivaranjani, P., & Senthilkumar, A. (2015). 3D VLSI non-slicing floorplanning using modified corner list representation. Indian Journal of Science and Technology, 8, 1. Sivaranjani, P., & Senthilkumar, A. (2015). 3D VLSI non-slicing floorplanning using modified corner list representation. Indian Journal of Science and Technology, 8, 1.
11.
go back to reference Zou, Q., Zhang, T., Kursun, E., & Xie, Y. (2013). Thermomechanical stress-aware management for 3D IC designs. In Proceedings of the conference on design, automation and test in Europe (pp. 1255–1258). Zou, Q., Zhang, T., Kursun, E., & Xie, Y. (2013). Thermomechanical stress-aware management for 3D IC designs. In Proceedings of the conference on design, automation and test in Europe (pp. 1255–1258).
12.
go back to reference Sivaranjani, P., & Kumar, A. S. (2015). Thermal-aware non-slicing VLSI floorplanning using a smart decision-making PSO-GA based hybrid algorithm. Circuits, Systems, and Signal Processing, 34, 3521–3542.CrossRef Sivaranjani, P., & Kumar, A. S. (2015). Thermal-aware non-slicing VLSI floorplanning using a smart decision-making PSO-GA based hybrid algorithm. Circuits, Systems, and Signal Processing, 34, 3521–3542.CrossRef
14.
go back to reference Paramasivam, S., Athappan, S., Natrajan, E. D., & Shanmugam, M. (2016). Optimization of thermal aware VLSI non-slicing floorplanning using hybrid particle swarm optimization algorithm-harmony search algorithm. Circuits and Systems, 7, 562.CrossRef Paramasivam, S., Athappan, S., Natrajan, E. D., & Shanmugam, M. (2016). Optimization of thermal aware VLSI non-slicing floorplanning using hybrid particle swarm optimization algorithm-harmony search algorithm. Circuits and Systems, 7, 562.CrossRef
15.
go back to reference Li, C.-R., Mak, W.-K., & Wang, T.-C. (2012). Fast fixed-outline 3-D IC floorplanning with TSV co-placement. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21, 523–532.CrossRef Li, C.-R., Mak, W.-K., & Wang, T.-C. (2012). Fast fixed-outline 3-D IC floorplanning with TSV co-placement. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21, 523–532.CrossRef
16.
go back to reference Lin, J.-M., & Yang, J.-A. (2017). Routability-driven TSV-aware floorplanning methodology for fixed-outline 3-D ICs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 36, 1856–1868.CrossRef Lin, J.-M., & Yang, J.-A. (2017). Routability-driven TSV-aware floorplanning methodology for fixed-outline 3-D ICs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 36, 1856–1868.CrossRef
Metadata
Title
Floor Planning of 3D IC Design Using Hybrid Multi-verse Optimizer
Authors
Sivakumar Pothiraj
Jeya Prakash Kadambarajan
Pandiaraj Kadarkarai
Publication date
16-02-2021
Publisher
Springer US
Published in
Wireless Personal Communications / Issue 4/2021
Print ISSN: 0929-6212
Electronic ISSN: 1572-834X
DOI
https://doi.org/10.1007/s11277-021-08166-z

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