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Published in:
2017 | OriginalPaper | Chapter
FPGA Implementation of Low Power Pipelined 32-Bit RISC Processor Using Clock Gating
Authors : R. Shashidar, R. Santhosh Kumar, A. M. MahalingaSwamy, M. Roopa
Published in: Proceedings of the International Conference on Data Engineering and Communication Technology
Publisher: Springer Singapore
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Abstract
Here we developed the RISC 32-bit processor architecture using Clock gating technique to perform logical memory and branching instruction. The different blocks are using to fetch, decode, execute, and memory read/write to execute four stage pipelining. The Harvard architecture used which contains memory space for data and program. To reduce the power of RISC core, clock gating technique is used in the architectural level as an effective low power method. The further enhancement of pipeline architecture can be done using Verilog and simulation is carried out using Model sim tool and implemented on FPGA board.