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2020 | OriginalPaper | Chapter

HCC: 100 Gbps AES-GCM Encrypted Inline DMA Transfers Between SGX Enclave and FPGA Accelerator

Authors : Luis Kida, Soham Desai, Alpa Trivedi, Reshma Lal, Vincent Scarlata, Santosh Ghosh

Published in: Information and Communications Security

Publisher: Springer International Publishing

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Abstract

This paper describes a Heterogeneous Confidential Computing (HCC) system composed of a CPU Trusted Computing Environment and a hardware accelerator. We implement two AES-GCM hardware engines with high-bandwidth and low-latency that are designed for end-to-end encryption of DMA transfers. Our solution minimizes changes to the hardware platform and to the application and SW stack. We prototyped and report the performance of protected image classification with proposed encrypted-DMA on an Intel Arria-10 FPGA.

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Literature
4.
go back to reference McKeen, F., et al.: Innovative instructions and software model for isolated execution. In: HASP 2013, pp. 1–8 (2013) McKeen, F., et al.: Innovative instructions and software model for isolated execution. In: HASP 2013, pp. 1–8 (2013)
5.
go back to reference Volos, S., Vaswani, K., Bruno, R.: Graviton: trusted execution environments on GPUs. In: Proceedings of the 13th USENIX Symposium on Operating Systems Design and Implementation (OSDI 2018) (2018) Volos, S., Vaswani, K., Bruno, R.: Graviton: trusted execution environments on GPUs. In: Proceedings of the 13th USENIX Symposium on Operating Systems Design and Implementation (OSDI 2018) (2018)
6.
go back to reference Jang, I., Kim, T., Sethumadhavan, S., Huh, J.: Heterogeneous isolated execution for commodity GPUs. In: ASPLOS 2019, 13–17 April (2019) Jang, I., Kim, T., Sethumadhavan, S., Huh, J.: Heterogeneous isolated execution for commodity GPUs. In: ASPLOS 2019, 13–17 April (2019)
7.
go back to reference Chung, E., et al.: Serving DNNs in real time at datacenter scale with project brainwave. IEEE Micro 38, 8–20 (2018)CrossRef Chung, E., et al.: Serving DNNs in real time at datacenter scale with project brainwave. IEEE Micro 38, 8–20 (2018)CrossRef
12.
go back to reference IEEE: IEEE Standard for Local and metropolitan area networks–Media Access Control (MAC) Security Amendment 1: Galois Counter Mode–Advanced Encryption Standard– 256 (GCM-AES-256) Cipher Suite.Satoh, A.: High-speed hardware architectures for authenticated encryption mode GCM. IEEE ISCAS (2006) IEEE: IEEE Standard for Local and metropolitan area networks–Media Access Control (MAC) Security Amendment 1: Galois Counter Mode–Advanced Encryption Standard– 256 (GCM-AES-256) Cipher Suite.Satoh, A.: High-speed hardware architectures for authenticated encryption mode GCM. IEEE ISCAS (2006)
13.
go back to reference Crenne, J., Cotret, P., Gogniat, G., Tessier, R., Diguet, J.: Efficient key-dependent message authentication in reconfigurable hardware. In: International Conference on Field Programmable Technology (FPT), pp. 1–6 (2011) Crenne, J., Cotret, P., Gogniat, G., Tessier, R., Diguet, J.: Efficient key-dependent message authentication in reconfigurable hardware. In: International Conference on Field Programmable Technology (FPT), pp. 1–6 (2011)
14.
go back to reference Abdellatif, K.M., Chotin-Avot, R., Mehrez, H.: Authenticated encryption on FPGAs from the static part to the reconfigurable part. Microprocess. Microsyst. 38, 526–538 (2014)CrossRef Abdellatif, K.M., Chotin-Avot, R., Mehrez, H.: Authenticated encryption on FPGAs from the static part to the reconfigurable part. Microprocess. Microsyst. 38, 526–538 (2014)CrossRef
17.
go back to reference Mathew, S., et al.: 53 Gbps native GF(24)2 composite-field AES-Encrypt/Decrypt accelerator for content-protection in 45 nm high-performance microprocessors. J. Solid-State Circuits 46(4), 767–776 (2011)CrossRef Mathew, S., et al.: 53 Gbps native GF(24)2 composite-field AES-Encrypt/Decrypt accelerator for content-protection in 45 nm high-performance microprocessors. J. Solid-State Circuits 46(4), 767–776 (2011)CrossRef
18.
go back to reference Gueron, S., Mathew, S.: Hardware implementation of AES using area-optimal polynomials for composite-field representation GF(2^4)^2 of GF(2^8). In: ARITH 2016, pp. 112–117 (2016) Gueron, S., Mathew, S.: Hardware implementation of AES using area-optimal polynomials for composite-field representation GF(2^4)^2 of GF(2^8). In: ARITH 2016, pp. 112–117 (2016)
19.
go back to reference Moradi, A., Poschmann, A., Ling, S., Paar, C., Wang, H., Paterson, K.G.: Pushing the limits: a very compact and a threshold implementation of AES. In: EUROCRYPT (2016) Moradi, A., Poschmann, A., Ling, S., Paar, C., Wang, H., Paterson, K.G.: Pushing the limits: a very compact and a threshold implementation of AES. In: EUROCRYPT (2016)
21.
go back to reference Baby Chellam, M., Natarajan, R.: AES hardware accelerator on FPGA with improved throughput and resource efficiency. Arab. J. Sci. Eng. 43, 6873–6890 (2018)CrossRef Baby Chellam, M., Natarajan, R.: AES hardware accelerator on FPGA with improved throughput and resource efficiency. Arab. J. Sci. Eng. 43, 6873–6890 (2018)CrossRef
23.
go back to reference Martinasek, Z., et al.: 200 Gbps hardware accelerated encryption system for FPGA network cards. In: Proceedings of the 2018 Workshop on Attacks and Solutions in Hardware Security (ASHES@CCS), pp. 11–17. ACM (2018) Martinasek, Z., et al.: 200 Gbps hardware accelerated encryption system for FPGA network cards. In: Proceedings of the 2018 Workshop on Attacks and Solutions in Hardware Security (ASHES@CCS), pp. 11–17. ACM (2018)
24.
go back to reference Buhrow, B., Fritz, K., Gilbert, B., Daniel, E.: A highly parallel AESGCM core for authenticated encryption of 400 Gb/s network protocols. In: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), pp. 1–7 (2015) Buhrow, B., Fritz, K., Gilbert, B., Daniel, E.: A highly parallel AESGCM core for authenticated encryption of 400 Gb/s network protocols. In: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), pp. 1–7 (2015)
25.
go back to reference Koteshwara, S., Das, A., Parhi, K.K.: FPGA implementation and comparison of AES-GCM and Deoxys authenticated encryption schemes. In: 2017 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–4 (2017) Koteshwara, S., Das, A., Parhi, K.K.: FPGA implementation and comparison of AES-GCM and Deoxys authenticated encryption schemes. In: 2017 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–4 (2017)
28.
go back to reference Vliegen, J., Reparaz, O., Mentens, N.: Maximizing the throughput of threshold-protected AES-GCM implementations on FPGA. In: 2017 IEEE 2nd International Verification and Security Workshop (IVSW), pp. 140–145 (2017) Vliegen, J., Reparaz, O., Mentens, N.: Maximizing the throughput of threshold-protected AES-GCM implementations on FPGA. In: 2017 IEEE 2nd International Verification and Security Workshop (IVSW), pp. 140–145 (2017)
29.
go back to reference Martinasek, Z., Hajny, J., Malina, L., Matousek, D.: Hardware-accelerated encryption with strong authentication. Secur. Protect. Inf. 1, 5 (2017) Martinasek, Z., Hajny, J., Malina, L., Matousek, D.: Hardware-accelerated encryption with strong authentication. Secur. Protect. Inf. 1, 5 (2017)
30.
go back to reference Lu, T., Kenny, R., Atsatt, S.: Secure device manager for Intel® Stratix® 10 Devices Provides FPGA and SoC Whitepaper Lu, T., Kenny, R., Atsatt, S.: Secure device manager for Intel® Stratix® 10 Devices Provides FPGA and SoC Whitepaper
Metadata
Title
HCC: 100 Gbps AES-GCM Encrypted Inline DMA Transfers Between SGX Enclave and FPGA Accelerator
Authors
Luis Kida
Soham Desai
Alpa Trivedi
Reshma Lal
Vincent Scarlata
Santosh Ghosh
Copyright Year
2020
DOI
https://doi.org/10.1007/978-3-030-61078-4_16

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