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Wireless Personal Communications
Published in: Wireless Personal Communications 4/2019

18-09-2018

Heuristic and Statistical Power Estimation Model for FPGA Based Wireless Systems

Authors: Gaurav Verma, Tarun Singhal, Rahul Kumar, Shivam Chauhan, Sushant Shekhar, Bishwajeet Pandey, D. M. Akbar Hussain

Published in: Wireless Personal Communications | Issue 4/2019

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Abstract

As the technology is advancing day by day, the need of high performance devices is also increasing. High performance is achieved at the expense of high power dissipation. Nowadays, field programmable gate arrays (FPGAs) are widely used in wireless communication systems due to their low non-recurring cost and high operating speed. There are many high performance applications (i.e., image processing, digital signal processing, wireless transceivers etc.) in which FPGAs are widely used. However, their complex architectures lead to high power consumption. Estimation of power in the early stage of the design flow would help designers to design the systems as per specified power budget. Therefore, two different approaches for power estimation are proposed in this paper. First is the heuristic approach based on back propagation neural network and second is the regression based statistical approach. It is observed that heuristic approach is better as compared regression in terms of power estimation of most of the digital circuits considered in this work.
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Literature
1.
Verma, G., Kumar, M., & Khare, V. (2017). Low power synthesis and validation of an embedded multiplier for FPGA based wireless communication system. Wireless Personal Communication, 95(2), 365–373.CrossRef
2.
Zhou, G., Guo, B., Gao, X., Ma, J., He, H., & Yan, Y. (2015). A FPGA power estimation model based on bp neural method. In International conference on intelligent information hiding and multimedia signal processing (pp. 251–254).
3.
Deng, L., Sobti, K., & Chakrabarti, C. (2011). Accurate models for estimating area and power of FPGA implementations. In Proceedings of IEEE international conference on acoustics speech and signal processing (pp. 1417–1420).
4.
Jevtic, R., & Carreras, C. (2010). Power estimation of embedded multiplier blocks in FPGAs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18(5), 835–839.CrossRef
5.
Choy, N. C. K., & Wilton, S. J. E. (2006). Activity-based power estimation and characterization of DSP and multiplier blocks in FPGAs. In Proceedings of FPT (pp. 253–256).
6.
Ell´eouet, D., Julien, N., Houzet, D., Cousin, J. G., & Martin, E. (2004). Power consumption characterization and modelling of embedded memories in Xilinx Virtex 400E FPGA. In Proceedings of the EUROMICRO systems on digital system design (pp. 394–401).
7.
Verma, G., Kumar, M., & Khare, V. (2015). Low power techniques for digital system design. Indian Journal of Science and Technology, 8(17), IPL063.
8.
Mishra, S., & Verma, G. (2013). Low power and area efficient implementation of BCD adder on FPGA. In Proceeding of IEEE international conference on signal processing and communication (pp. 461–465).
9.
Shinde, J., & Salankar, S. S. (2011). Clock gating-A power optimizing technique for VLSI circuits. In Proceedings of annual IEEE India conference (pp. 1–4).
10.
Castro, J., Parra, P., & Acosta, A. J., (2010). Optimization of clock-gating structures for low-leakage high-performance applications. In Proceedings of IEEE international symposium on efficient embedded computing (pp. 3220–3223).
11.
Teng, S. K., & Soin, N. (2010). Regional clock gate splitting algorithm for clock tree synthesis. In Proceedings of IEEE international conference on semiconductor electronics (pp. 131–134).
12.
Babighian, P., Benini, L., & Macii, E. (2005). A scalable algorithm for RTL insertion of gated clocks based on ODCs computation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(1), 29–42.CrossRef
13.
Huda, S., Mallick, M., & Anderson, J. H. (2009). Clock gating architectures for FPGA power reduction. In Proceedings of IEEE international conference on field programmable logic and applications (pp 112–118).
14.
Xilinx, San Jose, CA. (2003). Using embedded multipliers in Spartan-3 FPGA, Xilinx Appl. Note XAPP467, v.1.1.
15.
Kumar, T., Pandey, B., Das, T., & Chowdhry, B. S. (2014). Mobile DDR IO standard based high performance energy efficient portable ALU design on FPGA. Wireless Personal Communications, 76(3), 569–578.CrossRef
16.
Kumar, T., Pandey, B., Musavi, S. H. A., & Zaman, N. (2015). CTHS based energy efficient thermal aware image ALU design on FPGA. Wireless Personal Communications, 83(1), 671–696.CrossRef
Metadata
Title
Heuristic and Statistical Power Estimation Model for FPGA Based Wireless Systems
Authors
Gaurav Verma
Tarun Singhal
Rahul Kumar
Shivam Chauhan
Sushant Shekhar
Bishwajeet Pandey
D. M. Akbar Hussain
Publication date
18-09-2018
Publisher
Springer US
Published in
Wireless Personal Communications / Issue 4/2019
Print ISSN: 0929-6212
Electronic ISSN: 1572-834X
DOI
https://doi.org/10.1007/s11277-018-5927-7

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