Skip to main content
Disciplines
Automotive Business IT + Informatics Construction + Real Estate Electrical Engineering + Electronics Energy + Sustainability Insurance + Risk Finance + Banking Management + Leadership Marketing + Sales Mechanical Engineering + Materials
Events
DE
EN
Books
Journals
Topic Page
Marketing
Start single access now
Access for companies
EXTENDED SEARCH
Log in
Top
Published in:
Characterization of Fuzzy Tree Searches: A Perspective Note Read chapter Read first chapter

2015 | OriginalPaper | Chapter

High-performance Current Mode Receiver Design for On-chip VLSI Interconnects

Authors : Yash Agrawal, Rajeevan Chandel, Rohit Dhiman

Published in: Intelligent Computing and Applications

Publisher: Springer India

Log in

Activate our intelligent search to find suitable subject content or patents.

search-config
loading …

Abstract

This paper presents an efficient receiver design for on-chip current mode signaling (CMS) interconnects. The CMS interconnects using proposed receiver have 34 % lesser delay for interconnect length of 20 mm and around 3 times higher throughput at room temperature than that of conventional voltage mode signaling (VMS) interconnects. The analysis is performed for single-ended interconnects. The present work is useful for analyzing the effectiveness of voltage and current mode signaling techniques for on-chip interconnects. The simulations are performed for 180-nm technology node using Tanner EDA tool.

Dont have a licence yet? Then find out more about our products and how to get one now:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

inform now

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

inform now

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 340 Zeitschriften

aus folgenden Fachgebieten:

  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Versicherung + Risiko




Jetzt Wissensvorsprung sichern!

inform now
previous chapter Demonstration of GPGPU-Accelerated Computational Fluid Dynamic Calculations
next chapter CMOS Amplifier Design Using Simplified g m /I D Technique
Literature
1.
Md-Yusof, Z., Hani, M.K., Marsono, M.N., Husin, N.S.: An optimal VLSI routing algorithm with buffer insertion using iterative RLC model. In: Proceedings of IEEE International Conference on Circuits and Systems, pp. 48–53 (2012)
2.
Chandel, R., Sarkar, S., Agarwal, R.P.: An analysis of interconnect delay minimization by low-voltage repeater insertion. Microelectron. J. 38(4–5), 649–655 (2007). Elsevier ScienceCrossRef
3.
Dhiman, R., Chandel, R.: Sub-threshold delay and power analysis of complementary metal-oxide semiconductor buffer driven interconnect load for ultra low power applications. J. Low Power Electron. 8(1), 39–46 (2012)CrossRef
4.
Ismail, Y.I., Friedman, E.G.: Effect of inductance on the propagation delay and repeater insertion in VLSI circuits. IEEE Trans. Very Large Scale Integr. Syst. 8(2), 195–206 (2000)CrossRef
5.
Naeemi, A., Davis, J.A., Meindl, J.D.: Analysis and optimization for coplanar RLC lines for GSI global interconnections. IEEE Trans. Electron Devices 51(6), 985–994 (2004)CrossRef
6.
Yuan, F.: CMOS Current Mode Circuits for Data Communication. Springer, Heidelberg (2007)
7.
Dave, M., Jain, M., Baghini, M.S., Sharma, D.: A variation tolerant current-mode signaling scheme for on-chip interconnects. IEEE Trans. Very Large Scale Integr. Syst. 21(2), 342–353 (2013)CrossRef
8.
Kar, R., Reddy, K.R., Mal, A.K., Bhattacharjee, A.K.: An explicit approach for bandwidth evaluation of on-chip VLSI RC interconnects with current mode signaling technique. In: 2nd International Conference on Computing, Communication and Networking Technologies, pp. 1–4 (2010)
9.
Agrawal, Y., Chandel, R., Dhiman, R.: Design and analysis of efficient multilevel receiver for current mode interconnect system. In: 2014 IEEE Students’ Conference on Electrical, Electronics and Computer Science, Bhopal, pp. 1–6 (2014)
10.
Joshi, S., Sharma, D.: A novel low power multilevel current mode interconnect system. In: Emerging VLSI Technologies and Architectures (ISVLSI’06), pp. 1–6 (2006)
11.
12.
International technology roadmap for semiconductors (ITRS) (2014)
13.
Wong, S.C., Lee, G., Ma, D.: Modeling of interconnect capacitance, delay and crosstalk in VLSI. IEEE Trans. Semicond. Manuf. 13(1), 108–111 (2000)CrossRef
Metadata
Title
High-performance Current Mode Receiver Design for On-chip VLSI Interconnects
Authors
Yash Agrawal
Rajeevan Chandel
Rohit Dhiman
Copyright Year
2015
Publisher
Springer India
Book
Intelligent Computing and Applications

Print ISBN: 978-81-322-2267-5

Electronic ISBN: 978-81-322-2268-2

Copyright Year: 2015

DOI
https://doi.org/10.1007/978-81-322-2268-2_54

Premium Partner

    Image Credits