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Cluster Computing

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28-02-2018

High performance Viterbi decoder design

Authors: V. Kavitha, S. Mohanraj

Published in: Cluster Computing | Special Issue 3/2019

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Abstract

Viterbi decoder may be a regular module over correspondence framework in which energy also deciphering inactivity need aid demand. Register Exchange (RE) building design need the most reduced deciphering inactivity l. However, it is not suitable for correspondence framework due to its secondary force utilization. In this paper, it is recommended another SMU structural engineering which combines the idea of the trace-forward and also trace-back. Those deciphering inactivity of the suggested SMU calculation may be main L+M. Besides, we display a force productive building design for the recommended SMU algorithm. The recommended structural engineering is executed in Xilinx ISE 12. 3 for focus gadget may be Vertex6 FPGA. The control utilization of the suggested construction modeling is marginally higher over those 3-pointer.

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Title: High performance Viterbi decoder design
Authors: V. Kavitha
S. Mohanraj
Publication date: 28-02-2018
Publisher: Springer US
Published in: Cluster Computing / Issue Special Issue 3/2019
Print ISSN: 1386-7857
Electronic ISSN: 1573-7543
DOI: https://doi.org/10.1007/s10586-018-2295-8

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