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2018 | OriginalPaper | Chapter

1. Hybrid Data Converters

Author : Kostas Doris

Published in: Hybrid ADCs, Smart Sensors for the IoT, and Sub-1V & Advanced Node Analog Circuit Design

Publisher: Springer International Publishing

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Abstract

This work illustrates the broad and multidimensional nature of hybrid converters which reflects an optimal design policy going beyond the limiting boundaries of “the combination of known architectures” and the analog to digital converter itself. The analog to digital conversion extends from waves at the antenna interface to digital bits at the digital processor. This conversion is conditioned to the properties of CMOS technology through optimal combinations of techniques across multiple signal domains and hardware abstraction layers using modulation, redundancy, scheduling, on-chip information and other concepts. Dependent on the speed resolution domain, hybrid architectures take a different shape that matches to thermal noise or process technology limitations dominating in the corresponding domain.

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Doris, K.: Time interleaved analog-to-digital converters: an algorithmic melting pot. In: 2009 IEEE International Solid-State Circuits Conference (ISSCC), Jan 2009

Murmann, B.: ADC performance survey. http://www.stanford.edu/~murmann/adcsurvey.html

van Roermund, A.: Shifting the frontiers of analog and mixed-signal electronics. Advances in Electronics, vol. 2014 (2014)

Venca, A., et al.: A 0.076 mm² 12 b 26.5 mW 600 MS/s 4-way interleaved sub-ranging SAR- ΔΣ ADC with on-chip buffer in 28 nm CMOS. IEEE J. Solid State Circuits 51(12), 2951–2962 (2016)

Louwsma, S.M., et al.: A 1.35 GS/s, 10 b, 175 mW time-interleaved AD converter in 0.13 μm CMOS. IEEE J. Solid State Circuits 43(4), 778–786 (2008)

Verbruggen, B., et al.: A 2.6 mW 6 bit 2.2 GS/s fully dynamic pipeline ADC in 40 nm digital CMOS. IEEE J. Solid State Circuits 45(45), 2080–2090 (2010)

Cao, Z., et al.: A 32 mW 1.25 GS/s 6b 2b/Step SAR ADC in 0.13 μm CMOS. In: IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 542–543 (2008)

Wei, H., et al.: A 0.024 mm² 8b 400MS/s SAR ADC with 2b/Cycle and resistive DAC in 65 nm CMOS. In: IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 188–190 (2011)

Ding, M., et al.: A 5bit 1GS/s 2.7 mW 0.05 mm² asynchronous digital slope ADC in 90 nm CMOS for IR UWB radio. In: 2012 IEEE Radio Frequency Integrated Circuits Symposium, pp. 487–490, June 2012

10.

Liu, C.C., et al.: A 12 bit 100 MS/s SAR-assisted digital-slope ADC. IEEE J. Solid State Circuits 51(12), 2941–2950 (2016)CrossRef

11.

Harsener, M., et al.: A 14b 40 MS/s redundant SAR ADC with 480 MHz clock in 0.13 μm CMOS. In: IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 248–249 (2007)

12.

Hurrel, C., et al.: An 18b 12.5 MHz ADC with 93 dB SNR. In: IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 378–379 (2010)

13.

Fredenburg, J., Flynn, M.: A 90MS/s 11MHz bandwidth 62dB SNDR noise-shaping SAR ADC. In: IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 468–471 (2012)

14.

Liu, C.-C., et al.: A 0.46 mW 5MHz-BW 79.7 dB SNDR noise-shaping SAR ADC with dynamic-amplifier-based FIR-IIR Filter. In: 2017 IEEE International Solid-State Circuits Conference (ISSCC), pp. 466–467, Jan 2017

15.

Shu, Y.S., et al.: An oversampling SAR ADC with DAC mismatch error shaping achieving 105 dB SFDR and 101 dB SNDR over 1 kHz BW in 55 nm CMOS. IEEE J. Solid State Circuits 51(12), 2928–2940 (2016)CrossRef

16.

Xu, H., et al.: A 78.5dB-SNDR radiation- and metastability-tolerant two-step split SAR ADC operating up to 75MS/s with 24.9 mW power consumption in 65 nm CMOS. In: 2017 IEEE International Solid-State Circuits Conference (ISSCC), pp. 477–477, Jan 2017

17.

Ginsburg, B.P., Chandrakasan, A.P.: Highly interleaved 5-bit, 250-MSample/s, 1.2-mW ADC with redundant channels in 65-nm CMOS. IEEE J. Solid State Circuits 43(12), 2641–2650 (2008)

18.

Janssen, E., et al.: An 11b 3.6GS/s time-interleaved SAR ADC in 65 nm CMOS. In: 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 464–465, Feb 2013

19.

Kuttner, F.: A 1.2V 10b 20 MSample/s non-binary successive approximation ADC in 0.13 μm CMOS. In: IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 176–177 (2002)

20.

Boyacigiller, Z., et al.: An error-correcting 14b/20ps CMOS A/D converter. In: IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 62–63 (1981)

21.

Draxelmayr, D.: A self calibration technique for redundant A/D converters providing 16b accuracy. In: IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 204–205 (1988)

22.

Liu, W., et al.: A 12b 22.5/45MS/s 3.0 mW 0.059 mm² CMOS SAR ADC achieving over 90 dB SFDR. In: IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 380–381 (2010)

23.

Doris, K., et al.: A 480 mW 2.6GS/s 10b 65 nm time-interleaved ADC with 48.5 dB SNDR up to Nyquist. In: IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 180–182 (2011)

24.

Chen, S.-W.M., Brodersen, R.W.: A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS. IEEE J. Solid State Circuits 41(12), 731–740 (2006)

25.

Craninckx, J., Van der Plas, G.: A 65J/conversion-step 0-to-50MS/s 0-to-0.7 mW 9b charge-sharing SAR ADC in 90 nm digital CMOS. In: IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 246–247 (2007)

26.

Harpe, P., et al.: A 30fJ/Conversion-Step 8b 0-to-10MS/s asynchronous SAR ADC in 90 nm CMOS. In: IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 387–389 (2010)

27.

Verbruggen, B., Iriguchi, M., Craninckx, J.: A 1.7 mW 11b 250MS/s 2x interleaved fully dynamic pipelined SAR ADC in 40 nm Digital CMOS. In: IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 466–469 (2012)

28.

van der Goes, F., et al.: A 1.5 mW 68 dB SNDR 80 Ms/s 2x interleaved pipelined SAR ADC in 28 nm CMOS. IEEE J. Solid State Circuits 49(12), 2835–2845 (2014)

29.

Gupta, S., et al.: A 1GS/s 11b time-interleaved ADC with 55-dB SNDR, 250 mW power realized by a high bandwidth scalable time-interleaved architecture. IEEE J. Solid State Circuits 41, 2650–2657 (2006)CrossRef

30.

Greshishchev, Y., et al.: A 40GS/s 6b ADC in 65 nm CMOS. In: IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 390–391 (2010)

31.

Doris, K., et al.: Interleaving of sar adcs in deep submicron CMOS technology. Advances in Analog and RF IC Design for Wireless Communication Systems, 1st edn. Elsevier. ISBN:9780123983268

32.

Kull, L., et al.: 22.1 A 90GS/s 8b 667 mW 64x; interleaved SAR ADC in 32 nm digital SOI CMOS. In: 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 378–379, Feb 2014

33.

Duan, Y., Alon, E.: A 12.8 GS/s time-interleaved ADC with 25 GHz effective resolution bandwidth and 4.6 ENOB. IEEE J. Solid State Circuits 49(8), 1725–1738 (2014)

34.

Wu, J., et al.: A 4GS/s 13b pipelined ADC with capacitor and amplifier sharing in 16nm CMOS. In: 2016 IEEE International Solid-State Circuits Conference (ISSCC), pp. 466–467, Jan 2016

35.

Wu, J., et al.: A 5.4GS/s 12b 500 mW pipeline ADC in 28 nm CMOS. In: 2013 Symposium on VLSI Circuits, pp. C92–C93, June 2013

36.

Kull, L., et al.: A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14 nm CMOS FinFet. In: 2017 IEEE International Solid-State Circuits Conference (ISSCC), pp. 474–476, Jan 2017

37.

Vaz, B., et al.: A 13b 4GS/s digital assisted dynamic 3-stage asynchronous pipelined-SAR ADC. In: 2017 IEEE International Solid-State Circuits Conference (ISSCC), pp. 476–477, Jan 2017

38.

Su, S., Chen, M.S.W.: A 12b 2GS/s dual-rate hybrid DAC with pulsed timing-error pre-distortion and in-band noise cancellation achieving > 74dBc SFDR up to 1 GHz in 65 nm CMOS. In: 2016 IEEE International Solid-State Circuits Conference (ISSCC), pp. 456–457, Jan 2016

39.

Olieman, E., et al.: A 110 mW, 0.04 mm², 11gs/s 9-bit interleaved DAC in 28 nm fdsoi with 50 dB SFDR across nyquist. In: 2014 Symposium on VLSI Circuits Digest of Technical Papers, June 2014, pp. 1–2

40.

Bechthum, E., et al.: A wideband RF mixing-DAC achieving IMD lt; -82 DBC up to 1.9 GHz. IEEE J. Solid State Circuits 51(6), 1374–1384 (2016)

41.

McCreary, J., Gray, P.: All-MOS charge redistribution analog-to-digital conversion techniques. IEEE J. Solid State Circuits 10(6), 371–379 (1975)CrossRef

42.

Alpman, E., et al.: A 1.1V 50 mW 2.5GS/s 7b time-interleaved C-2C SAR ADC in 45 nm LP digital CMOS. In: IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 76–77, 77a (2009)

43.

Kramer, M.J., et al.: A 14 b 35 MS/s SAR ADC achieving 75 dB SNDR and 99 dB SFDR with loop-embedded input buffer in 40 nm CMOS. IEEE J. Solid State Circuits 50(12), 2891–2900 (2015)CrossRef

44.

Poulton, K., et al.: A 7.2-GSa/s, 14-bit or 12-GSa/s, 12-bit DAC in a 165-GHz fT BiCMOS process. In: 2011 Symposium on VLSI Circuits – Digest of Technical Papers, pp. 62–63, June 2011

45.

Hershberg, B., et al.: Ring amplifiers for switched capacitor circuits. IEEE J. Solid-State Circuits 47(12), 2928–2942 (2012)CrossRef

46.

van Elzakker, M., et al.: A 10-bit charge-redistribution ADC consuming 1.9μW at 1MS/s. IEEE Journal of Solid-State Circuits 45(5), 1007–1015 (2010)

47.

Breems, L., et al.: A 2.2 GHz continuous-time ΔΣ ADC with 102 dBc THD and 25 MHz bandwidth. IEEE J. Solid-State Circuits 51(12), 2906–2916 (2016)

48.

Harpe, P., et al.: A 7-to-10b 0-to-4MS/s flexible SAR ADC with 6.5-to-16fJ/conversion-step. In: IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 472–475 (2012)

49.

Kramer, M.J., et al.: A 14-bit 30-MS/s 38-mW SAR ADC using noise filter gear shifting. IEEE Trans. Circuits Syst. Express Briefs 64(2), 116–120 (2017)CrossRef

50.

Yip, M., Chandrakasan, A.: A resolution-reconfigurable 5-to-10b 0.4-to-1V power scalable SAR ADC. In: IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 190–191 (2011)

51.

Tang, Y., et al.: A 14 bit 200 MS/s DAC with SFDR > 78 dBc, im3 < −83 dBc and NSD < −163 dbm/Hz across the whole Nyquist band enabled by dynamic-mismatch mapping. IEEE J. Solid State Circuits 46(6), 1371–1381 (2011)CrossRef

52.

de Vel, H.V., et al.: 11.7 a 240 mW 16b 3.2gs/s DAC in 65 nm CMOS with − 80 dBc im3 up to 600 MHz. In: 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 206–207, Feb 2014

53.

Lin, Y.: et al.: An 11b 1GS/s ADC with parallel sampling architecture to enhance SNDR for multi-carrier signals. In: 2013 Proceedings of the ESSCIRC (ESSCIRC), pp. 121–124, Sept 2013

54.

Greshishchev, Y.: CMOS ADCs for optical communications. In: Proceedings of the 20th Workshop on Advances in Analog Circuit Design (AACD), Apr 2012

55.

Brandolini, M., et al.: 26.6 A 5GS/S 150 mW 10b SHA-less pipelined/SAR hybrid ADC in 28 nm CMOS. In: 2015 IEEE International Solid-State Circuits Conference – (ISSCC) Digest of Technical Papers, pp. 1–3, Feb 2015

56.

Devarajan, S., et al.: A 12b 10GS/s interleaved pipeline ADC in 28 nm CMOS technology. In: 2017 IEEE International Solid-State Circuits Conference (ISSCC), pp. 288–289, Jan 2017

57.

Ali, A.M.A., et al.: A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither. In: 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), pp. 1–2, June 2016

58.

Kapusta, R., et al.: A 14b 80 Ms/s SAR ADC with 73.6 db SNDR in 65 nm CMOS. IEEE J. Solid State Circuits 48(12), 3059–3066 (2013)

59.

Gonen, B., et al.: 15.7 A 1.65 mW 0.16 mm2 dynamic zoom-ADC with 107.5 dB DR in 20 kHz BW. In: 2016 IEEE International Solid-State Circuits Conference (ISSCC), pp. 282–283, Jan 2016

Title: Hybrid Data Converters
Author: Kostas Doris
Publisher: Springer International Publishing
Book: Hybrid ADCs, Smart Sensors for the IoT, and Sub-1V & Advanced Node Analog Circuit Design
Print ISBN: 978-3-319-61284-3

Electronic ISBN: 978-3-319-61285-0

Copyright Year: 2018
DOI: https://doi.org/10.1007/978-3-319-61285-0_1