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2024 | OriginalPaper | Chapter

Implementation of Energy Efficient Full Adder for Arithmetic Application

Authors : Md. Shahbaz Hussain, Jyoti Kandpal, Mohd Hasan, Koushik Guha

Published in: Micro and Nanoelectronics Devices, Circuits and Systems

Publisher: Springer Nature Singapore

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Abstract

This study reports the implementation of a hybrid CMOS-based 1-bit full adder (FA) circuit. The need for noise robustness, better drivability and low-energy operation for deep submicron encourage the examination of the hybrid design style. Hybrid CMOS design techniques are utilized to propose new full-featured adders with the desired performance. Module I (XOR-XNOR) generates the XOR-XNOR output simultaneously. Module II and Module III are implemented using the PTL and TG logic. In this work, 16 nm FinFET technology is used to implement a novel design of hybrid FA. The proposed design shows 29.37–71.90% and 38.96–81.56% improvement in power consumption and PDP, respectively.

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Title: Implementation of Energy Efficient Full Adder for Arithmetic Application
Authors: Md. Shahbaz Hussain
Jyoti Kandpal
Mohd Hasan
Koushik Guha
Publisher: Springer Nature Singapore
Book: Micro and Nanoelectronics Devices, Circuits and Systems
Print ISBN: 978-981-9944-94-1

Electronic ISBN: 978-981-9944-95-8

Copyright Year: 2024
DOI: https://doi.org/10.1007/978-981-99-4495-8_20