Implementation of high speed and area efficient MAC unit for industrial applications

In today’s digital processors the everlasting demand is the enhancement of knack in processors to handle the complexities resulted in the incorporation of some of the processor cores in a single chip. Then more the load on the processor is not fewer in the primary system. This load can be minimized by augmenting the central processor with the co-processors, which are made up to work with a particular type of functions like graphics, signal processing, numeric computation, etc. Hence, in which the multiplier and accumulator (MAC) unit is most leading co-processor and toil as the heart of the digital signal processors. Faster processes are of great significance in MAC unit. Ultimate digital signal processing algorithms depend significantly on multiply and accumulator (MAC) performance. Hence after a deep study and investigation, we found that the proficiency of Urdhva-tiryagbhyam Vedic multiplication algorithm found to be superior in comparison with other conventional multipliers. The rapidity of multiplication and addition governs the execution speed and performance of entire setup. Here we will design and analyze the performance of MAC unit, and thus, the delay and area parameters are optimized using various multipliers such as Array, Wallace, Vedic multipliers, etc. The proposed method is designed using Xilinx 12.3 and tested using the Virtex5-XC5VLX110T device.