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2017 | OriginalPaper | Chapter
1. Introduction to HDL
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Abstract
This chapter discusses the digital logic design evolution and the basic ASIC design flow. The chapter describes the necessity of ASIC SOC prototype. The comparison of ASIC and FPGA implementation is described in this chapter. The chapter even discusses the need of HDL and VHDL different modeling styles using the small gate count example. This chapter is useful to the HDL beginners to understand about the difference between high-level language and HDL modeling styles.