Advertisement
Published in:
2014 | OriginalPaper | Chapter
1. Introduction
Author : Ashok B. Mehta
Published in: SystemVerilog Assertions and Functional Coverage
Publisher: Springer New York
Activate our intelligent search to find suitable subject content or patents.
Select sections of text to find matching patents with Artificial Intelligence. powered by
Select sections of text to find additional relevant content using AI-assisted search. powered by
Abstract
As is well known in the industry, the design complexity at 28 nm node and below is exploding. Small form factor requirements and conflicting demands of high performance and low power and small area result in ever so complex design architecture. Multi-core, multi-threading and Power, Performance and Area (PPA) demands exacerbate the design complexity and functional verification thereof.