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2006 | Book

INTRODUCTION Read chapter Read first chapter

IQ CALIBRATION TECHNIQUES FOR CMOS RADIO TRANSCEIVERS

Authors: Sao-Jie Chen, Yong-Hsiang Hsieh

Publisher: Springer Netherlands

Book Series : Analog Circuits and Signal Processing

Part of: Springer Professional "Wirtschaft+Technik" , Springer Professional "Technik"

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About this book

In the market of wireless communication, high data-rate transmission and high spectral efficiency have been the trend. The IEEE 802.11 a/g standards working at 5GHz/2.4GHz ISM bands can support data rate up to 54Mbits/s using OFDM modulation. The newly proposed 802.11n technology now uses 64-QAM to achieve higher spectral efficiency. The DVB and many other systems will also use QAM for its data transmission.

The cost of achieving this higher spectral efficiency using higher order QAM is that the transmitter and receiver requires a higher signal to noise ratio (SNR) with the same level of error rate performance (relative to a baseline BPSK, QPSK and other systems). One of the dominant vectors on SNR degradation is I/Q image rejection (I/Q gains and phases imbalance).

There are a lot of factors that degrade the matching of gains and phases between I/Q signals: the instinct layout mismatch, the random mismatch of the devices, the different temperatures over the I/Q signal paths. IQ Calibration Techniques For CMOS Radio Transceivers describes a fully-analog compensation technique without baseband circuitry to control the calibration process. This book will use an 802.11g transceiver design as an example to give a detailed description on the I/Q gains and phases imbalance auto-calibration mechanism.

Table of Contents

Frontmatter
1. INTRODUCTION
Abstract
This chapter will present the standards of different wireless applications and describe the development of wireless products in the 21st century. Then more detailed and comparative explanation on a series of IEEE 802.11 standards will be shown. Since IEEE 802.11g is the best choice considering performance and cost now in the 802.11x series, the difficulties faced on IEEE 802.11g transceiver design will be discussed, especially the I/Q mismatch in quadrature modulator and demodulator.
Sao-Jie Chen, Yong-Hsiang Hsieh
2. TRANSCEIVER ARCHITECTURE DESIGN
Abstract
The first section of this chapter compares the pluses and minuses of different receiver architectures. A transceiver includes two components: a receiver and a transmitter, but this chapter will only make comparisons to receiver, because the characteristic of transmitters are similar to receivers. The second section describes the reason of architecture selection. The third section gives a brief description on the selected transceiver architecture. The fourth section discusses the IF frequency consideration. The receiver link budget and design parameters will be mentioned in the fifth section of this chapter. Finally, the transmitter link budget design and design parameters will be presented in the last section.
Sao-Jie Chen, Yong-Hsiang Hsieh
3. I/Q MODULATOR AND DEMODULATOR DESIGN
Abstract
The first section of this chapter reviews the architecture of I/Q modulator and demodulator. To reduce the total die area, we will discuss how the IF VGA, modulator and demodulator circuits are re-used in the second section. The final section describes the proposed DC offset cancellation loop in demodulator.
Sao-Jie Chen, Yong-Hsiang Hsieh
4. AN AUTO-I/Q CALIBRATED MODULATOR
Abstract
The inphase/quadraure signal processing vastly utilized in present communication transceiver faces a common issue of amplitude matching and phase matching in the inphase and the quadrature branches, and this I/Q imbalance is one of the performance bottlenecks in a transceiver. The gain and phase mismatches between inphase signal and quadrature signal degrade the signal-to-noise ratio, therefore raising the bit error rate. Thus, it is necessary to establish an auto-calibration mechanism in a transceiver, reducing the gain imbalance and phase error contributed by the I and Q paths. This chapter will describe the modulator auto-calibration mechanism first and the calibration mechanism in a demodulator will be showed in next chapter.
Sao-Jie Chen, Yong-Hsiang Hsieh
5. AN AUTO-I/Q CALIBRATED DEMODULATOR
Abstract
To calibrate the demodulator, a single-tone test signal is also needed. The first section of this chapter describes how to generate this test signal in the modulator. The second section shows the auto-calibration mechanism and calibration circuits design. The error on calibration results caused by the non-ideal calibration circuits and the test signal, and the solution on eliminating the error both will be shown in this section. The final section of this chapter will show the measurement results on the RX modulator calibration.
Sao-Jie Chen, Yong-Hsiang Hsieh
6. SYSTEM MEASUREMENT RESULT
Abstract
A fully integrated 802.11g transceiver IC is fabricated in a 0.25 μ 1P5M CMOS technology. Its die microphotograph is shown in Figure 6.1 and typical measurement results of the transmitter are summarized in Section 6.1 and the results of the receiver are summarized in Section 6.2. The total die area is 10.2mm2 (3mm x 3.4mm) and is housed in a 48-pin QFN package. A Printed Circuit Board (PCB) test board is shown in Figure 6.2; all the characteristic results are measured from this PCB.
Sao-Jie Chen, Yong-Hsiang Hsieh
7. CONCLUSION
Abstract
In the market of wireless local area network (WLAN), high data-rate transmission has been the trend. IEEE 802.11g standard works at 2.4GHz ISM band and supports data rates up to 54Mbits/s using OFDM modulation. To achieve the desired performance upper bound, it is crucial to deliver a close match of I and Q signals in both the modulator and the demodulator.
Sao-Jie Chen, Yong-Hsiang Hsieh
Backmatter
Metadata
Title
IQ CALIBRATION TECHNIQUES FOR CMOS RADIO TRANSCEIVERS
Authors
Sao-Jie Chen
Yong-Hsiang Hsieh
Copyright Year
2006
Publisher
Springer Netherlands
Electronic ISBN
978-1-4020-5083-1
Print ISBN
978-1-4020-5082-4
DOI
https://doi.org/10.1007/1-4020-5083-6