LIMES: Logic Locking on Interleaved Memory for Enhanced Security

Globalization and increasing distribution of IC supply chain have resulted in various third parties having a key to precious intellectual property or the physical integrated circuit and therefore information can be exploited. Information security is the practice of safeguarding information by minimizing information risks. It is required to scale down the danger of unauthorized information disclosure, modification, and destruction. Hardware security threats have been observed at several levels of the IC supply chain. To protect the hardware from potential attacks, there are various design-for-security (DFS) techniques. Interleaved memory with logic locking techniques for information security is proposed in this paper. Interleaved memory is a solution for random arrangement and logic locking is needed to interrupt the chain and to protect the data by restricting its access to authorized users. It is a versatile and easy-to-integrate solution that needs only trusted designers. The approach proposed in this paper compares the Hamming distance (HD) and Levenshtein distance (LD) and BER obtained for random logic locking (RLL) and weighted logic locking (WLL) on the interleaved memory. From the results obtained, it can be concluded that weighted logic locking on interleaved memory provides better security.