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2011 | OriginalPaper | Chapter

5. Low-Power ADCs for Bio-Medical Applications

Authors : J. Craninckx, G. Van der Plas

Published in: Bio-Medical CMOS ICs

Publisher: Springer US

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Abstract

In this chapter, recent innovations reducing power consumption in A/D converters will be discussed. Indeed, in many applications the function performing a conversion from the analog continuous-time domain to the discrete-time digital domain takes a large proportion of the power consumption. Especially for biomedical systems an aggressive reduction in power consumption of all blocks including A/D converters opens up a window for higher performance and more versatile solutions.

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Literature
1.
go back to reference van de Plassche R (2003) CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, 2nd edn. Kluwer, DordrechtMATH van de Plassche R (2003) CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, 2nd edn. Kluwer, DordrechtMATH
2.
go back to reference Walden RH (1999) Analog-to-digital converter survey and analysis. J Select Areas Commun 17(4):539–550, April 1999CrossRef Walden RH (1999) Analog-to-digital converter survey and analysis. J Select Areas Commun 17(4):539–550, April 1999CrossRef
3.
go back to reference Craninckx J, Van der Plas G (2007) A 65 fJ/Conversion-Step 0-to-50 Ms/s 0-to-0.7 mW 9b Charge sharing SAR ADC in 90 nm Digital CMOS. ISSCC Dig Tech Papers, pp. 246–247, Feb 2007 Craninckx J, Van der Plas G (2007) A 65 fJ/Conversion-Step 0-to-50 Ms/s 0-to-0.7 mW 9b Charge sharing SAR ADC in 90 nm Digital CMOS. ISSCC Dig Tech Papers, pp. 246–247, Feb 2007
4.
go back to reference van Elzakker M, van Tuijl E,.Geraedts P, Schinkel D, Klumperink E, Nauta B (2008) A 1.9 μW 4.4fj/conversion-step 10b 1 ms/s charge-redistribution ADC. In: Proceedings of Digest of Technical Papers. IEEE International Solid-State Circuits Conference ISSCC 2008, p 244–610, 3–7 Feb 2008 van Elzakker M, van Tuijl E,.Geraedts P, Schinkel D, Klumperink E, Nauta B (2008) A 1.9 μW 4.4fj/conversion-step 10b 1 ms/s charge-redistribution ADC. In: Proceedings of Digest of Technical Papers. IEEE International Solid-State Circuits Conference ISSCC 2008, p 244–610, 3–7 Feb 2008
5.
go back to reference Van der Plas G, Verbruggen B (2008) A 150 MS/s 133 μW 7 bit ADC in 90 nm digital CMOS. IEEE J Solid-State Circuits, 43(12):2631–2640, Dec 2008CrossRef Van der Plas G, Verbruggen B (2008) A 150 MS/s 133 μW 7 bit ADC in 90 nm digital CMOS. IEEE J Solid-State Circuits, 43(12):2631–2640, Dec 2008CrossRef
6.
go back to reference Agnes A, Bonizzoni E, Malcovati P, Maloberti F (2008) A 9.4-ENOB 1 V 3.8 μW 100 kS/s SAR ADC with time-domain comparator. In: Proceedings of Digest of Technical Papers. IEEE International Solid-State Circuits Conference ISSCC 2008, pages 246–610, 3–7 Feb 2008 Agnes A, Bonizzoni E, Malcovati P, Maloberti F (2008) A 9.4-ENOB 1 V 3.8 μW 100 kS/s SAR ADC with time-domain comparator. In: Proceedings of Digest of Technical Papers. IEEE International Solid-State Circuits Conference ISSCC 2008, pages 246–610, 3–7 Feb 2008
7.
go back to reference Boulemnakher M, Andre E, Roux J, Paillardet F (2008) A 1.2 V 4.5 mW 10b 100 MS/s pipeline ADC in a 65 nm CMOS. In: Proceedings Digest of Technical Papers. IEEE International Solid-State Circuits Conference ISSCC 2008, pages 250–611, 3–7 Feb 2008 Boulemnakher M, Andre E, Roux J, Paillardet F (2008) A 1.2 V 4.5 mW 10b 100 MS/s pipeline ADC in a 65 nm CMOS. In: Proceedings Digest of Technical Papers. IEEE International Solid-State Circuits Conference ISSCC 2008, pages 250–611, 3–7 Feb 2008
8.
go back to reference Giannini V, Nuzzo P, Chironi V, Baschirotto A, Van der Plas G, Craninckx J (2008) A 820 μW 9b 40 MS/s Noise Tolerant Dynamic SAR ADC in 90 nm Digital CMOS. ISSCC Digest. of Technical Papers, pp. 238-239, Feb 2008 Giannini V, Nuzzo P, Chironi V, Baschirotto A, Van der Plas G, Craninckx J (2008) A 820 μW 9b 40 MS/s Noise Tolerant Dynamic SAR ADC in 90 nm Digital CMOS. ISSCC Digest. of Technical Papers, pp. 238-239, Feb 2008
9.
go back to reference Abo M, Gray P (1999) A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter. IEEE J Solid State Circuits 34(5):599-606, May 1999CrossRef Abo M, Gray P (1999) A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter. IEEE J Solid State Circuits 34(5):599-606, May 1999CrossRef
10.
go back to reference Van der Plas G, Decoutere S, Donnay S (2006) A 0.16 pF/conversion-step 2.5 mW 1.25 GS/s 4b ADC in a 90 nm digital CMOS process. ISSCC Digest of Technical Papers, pp. 566–567, Feb 2006 Van der Plas G, Decoutere S, Donnay S (2006) A 0.16 pF/conversion-step 2.5 mW 1.25 GS/s 4b ADC in a 90 nm digital CMOS process. ISSCC Digest of Technical Papers, pp. 566–567, Feb 2006
11.
go back to reference Van den Bosch A (2004) Static and dynamic performance limitations for high speed D/A converters. ISBN 9781402077616, Springer Van den Bosch A (2004) Static and dynamic performance limitations for high speed D/A converters. ISBN 9781402077616, Springer
12.
go back to reference Scholtens P, Vertregt M (2002) A 6-b 1.6-Gsamples Flash ADC in 0.18 μm CMOS using averaging termination. IEEE JSSC 37(12):1599–1609, Dec 2002 Scholtens P, Vertregt M (2002) A 6-b 1.6-Gsamples Flash ADC in 0.18 μm CMOS using averaging termination. IEEE JSSC 37(12):1599–1609, Dec 2002
13.
go back to reference Lin J, Haroun B (2002) An embedded 0.8 V/480 μW 6B/22 MHz flash ADC in 0.13-μm Digital CMOS process using a nonlinear double interpolation technique. IEEE JSSC 37(12)1610–1617, Dec 2002 Lin J, Haroun B (2002) An embedded 0.8 V/480 μW 6B/22 MHz flash ADC in 0.13-μm Digital CMOS process using a nonlinear double interpolation technique. IEEE JSSC 37(12)1610–1617, Dec 2002
14.
go back to reference Draxelmayr D (2004) A 6b 600 MHz 10 mW ADC Array in Digital 90 nm CMOS. IEEE digest of ISSCC 2004, paper 14.7 Draxelmayr D (2004) A 6b 600 MHz 10 mW ADC Array in Digital 90 nm CMOS. IEEE digest of ISSCC 2004, paper 14.7
15.
go back to reference Ginsburg BP, Chandrakasan AP (2008) Highly Interleaved 5b 250 MS/s ADC with redundant channels in 65 nm CMOS. ISSCC Digest of Technical Papers, pp. 240–241, Feb. 2008 Ginsburg BP, Chandrakasan AP (2008) Highly Interleaved 5b 250 MS/s ADC with redundant channels in 65 nm CMOS. ISSCC Digest of Technical Papers, pp. 240–241, Feb. 2008
16.
go back to reference Chen S, Brodersen R (2006) A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS. IEEE J Solid-State Circuits 41(12)2669–2680, Dec 2006CrossRef Chen S, Brodersen R (2006) A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS. IEEE J Solid-State Circuits 41(12)2669–2680, Dec 2006CrossRef
17.
go back to reference Brooks L, Lee H-S (2007) A zero-crossing-based 8-bit 200 MS/s pipelined ADC. IEEE JSSC 42(12):1896–1906, Dec 2007 Brooks L, Lee H-S (2007) A zero-crossing-based 8-bit 200 MS/s pipelined ADC. IEEE JSSC 42(12):1896–1906, Dec 2007
18.
go back to reference Van der Plas G, Verbruggen B (2008) A 150 MS/s 133 μW 7b ADC in 90 nm digital CMOS Using a comparator-based asynchronous binary-search sub-ADC. IEEE Digest of ISSCC 2008, paper 12.3 Van der Plas G, Verbruggen B (2008) A 150 MS/s 133 μW 7b ADC in 90 nm digital CMOS Using a comparator-based asynchronous binary-search sub-ADC. IEEE Digest of ISSCC 2008, paper 12.3
19.
go back to reference Kobayashi T et al (1993) A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture. IEEE JSSC 28(4):523–527, April 1993 Kobayashi T et al (1993) A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture. IEEE JSSC 28(4):523–527, April 1993
20.
go back to reference Nuzzo P et al. (2008) Noise analysis of regenerative comparators for reconfigurable ADC architectures. IEEE Trans Circuits Sys I: Fundam Theory Appl 55(6): 1441–1454, July 2008CrossRefMathSciNet Nuzzo P et al. (2008) Noise analysis of regenerative comparators for reconfigurable ADC architectures. IEEE Trans Circuits Sys I: Fundam Theory Appl 55(6): 1441–1454, July 2008CrossRefMathSciNet
21.
go back to reference Nuzzo P et al. (2006) Efficient calibration through statistical behavioral modeling of a high-speed low-power ADC. Proceedings of PRIME, pp. 297–300, Jun 2006 Nuzzo P et al. (2006) Efficient calibration through statistical behavioral modeling of a high-speed low-power ADC. Proceedings of PRIME, pp. 297–300, Jun 2006
22.
go back to reference Daly D, Chandrakasan A (2008) A 6b 0.2-to-0.9 V highly digital flash ADC with comparator redundancy. ISSCC Digest of Technical Papers, pp. 554–555, Feb 2008 Daly D, Chandrakasan A (2008) A 6b 0.2-to-0.9 V highly digital flash ADC with comparator redundancy. ISSCC Digest of Technical Papers, pp. 554–555, Feb 2008
23.
go back to reference Petrescu V et al. (2006) A signal-integrity self-test concept for debugging nanometer CMOS ICs. ISSCC Digest of Technical Papers, pp. 544–545, Feb 2006 Petrescu V et al. (2006) A signal-integrity self-test concept for debugging nanometer CMOS ICs. ISSCC Digest of Technical Papers, pp. 544–545, Feb 2006
24.
go back to reference McCreary J, Gray P (1975) All-MOS charge redistribution Analog-to-Digital conversion techniques—Part I. IEEE J Solid-State Circuits 10(6):371–379, Dec 1975CrossRef McCreary J, Gray P (1975) All-MOS charge redistribution Analog-to-Digital conversion techniques—Part I. IEEE J Solid-State Circuits 10(6):371–379, Dec 1975CrossRef
25.
go back to reference Verbruggen B et al. (2008) A 2.2 mW 5b 1.75 GS/s Folding Flash ADC in 90 nm Digital CMOS. ISSCC Digest of Technical Papers, pp. 252–253, Feb 2008 Verbruggen B et al. (2008) A 2.2 mW 5b 1.75 GS/s Folding Flash ADC in 90 nm Digital CMOS. ISSCC Digest of Technical Papers, pp. 252–253, Feb 2008
Metadata
Title
Low-Power ADCs for Bio-Medical Applications
Authors
J. Craninckx
G. Van der Plas
Copyright Year
2011
Publisher
Springer US
DOI
https://doi.org/10.1007/978-1-4419-6597-4_5